DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et al. (U.S. Patent No. 10,128,379).
Regarding to claim 12, Song teaches a semiconductor arrangement, comprising:
a first semiconductor material layer extending between a first source/drain region and a second source/drain region (Figs. 1-2, column 3, lines 19-20, first semiconductor material layer 120/left extending between first source/drain region and second source/drain region);
a second semiconductor material layer extending between a third source/drain region and a fourth source/drain region (Figs. 1-2, column 3, lines 19-20, second semiconductor material layer 120/right extending between third source/drain region and fourth source/drain region);
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a first gate dielectric layer surrounding the first semiconductor material layer and surrounding the second semiconductor material layer (Figs. 1-2; column 5, lines 56-60, inner dielectric layer of stack layer 110);
a second gate dielectric layer comprising a dielectric material different than the first gate dielectric layer and surrounding the first semiconductor material layer (Figs. 1-2; column 5, lines 56-60, outer dielectric layer of stack dielectric layer 110) such that the first gate dielectric layer is between the first semiconductor material layer and the second gate dielectric layer to separate the first semiconductor material layer from the second gate dielectric layer (the inner electric layer wraps around the first semiconductor material layer, which is a nanowire, the outer electric layer wraps around the inner electric layer, thus the first gate dielectric layer is between the first semiconductor material layer and the second gate dielectric layer to separate the first semiconductor material layer from the second gate dielectric layer);
a first gate electrode surrounding the first semiconductor material layer and in contact with the second gate dielectric layer (Figs. 1-2, first gate electrode 130/left surrounding the first semiconductor material layer 120/left and in contact with the second gate dielectric layer); and
a second gate electrode surrounding the second semiconductor material layer and in contact with the first gate dielectric layer (Figs. 1-2, second gate electrode 130/right surrounding the second semiconductor material layer120/right and in contact with first gate dielectric layer via the second gate dielectric layer. Please note that the claim does not require a direct contact).
Regarding to claim 13, Song teaches a third semiconductor material layer under the first semiconductor material layer (Fig. 2, there are three wires shown in the left stack, the third semiconductor material layer is the second wire from the top), wherein the first gate dielectric layer and the second gate dielectric layer surround the third semiconductor material layer (Fig. 2, dielectric stack 110 including first and second dielectric layers surround the third semiconductor material layer).
Regarding to claim 14, Song teaches a third semiconductor material layer under the second semiconductor material layer (Fig. 2, Fig. 2, there are three wires shown in the right stack, the third semiconductor material layer is the second wire from the top), wherein the first gate dielectric layer surrounds the third semiconductor material layer (Fig. 2, dielectric stack 110 including first surround the third semiconductor material layer).
Regarding to claim 15, Song teaches the second gate dielectric layer is between the second semiconductor material layer and the third semiconductor material layer (the inner electric layer wraps around the third semiconductor material layer, which is the center nanowire, the outer electric layer wraps around the inner electric layer, thus the second gate dielectric layer is between the second semiconductor material layer and the third semiconductor material layer).
Regarding to claim 16, Song teaches a cap layer (Fig. 2, element 150), wherein:
a first portion of the cap layer overlying the first semiconductor material layer is in contact with the second gate dielectric layer (Fig. 2, first portion 150/left of the cap layer overlying the first semiconductor material layer 120/left is in contact with the dielectric stack 110, thus in contact with the second gate dielectric layer), and
a second portion of the cap layer overlying the second semiconductor material layer is in contact with the first gate dielectric layer (Fig. 2, a second portion 150/right of the cap layer overlying the second semiconductor material layer 120/right is in contact with the dielectric stack 110, thus in contact with the first gate dielectric layer).
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Regarding to claim 17, Song teaches a semiconductor arrangement, comprising:
a first semiconductor material layer extending between a first source/drain region and a second source/drain region (Figs. 1-2, column 3, lines 19-20, first semiconductor material layer 120/left extending between first source/drain region and second source/drain region);
a second semiconductor material layer extending between a third source/drain region and a fourth source/drain region (Figs. 1-2, column 3, lines 19-20, second semiconductor material layer 120/right extending between third source/drain region and fourth source/drain region);
a first gate dielectric layer surrounding the first semiconductor material layer and surrounding the second semiconductor material layer (Figs. 1-2; column 5, lines 56-60, inner dielectric layer of stack layer 110);
a second gate dielectric layer comprising a dielectric material different than the first gate dielectric layer and surrounding the first semiconductor material layer (Figs. 1-2; column 5, lines 56-60, outer dielectric layer of stack dielectric layer 110) such that the first gate dielectric layer is between the first semiconductor material layer and the second gate dielectric layer to separate the first semiconductor material layer from the second gate dielectric layer (the inner electric layer wraps around the first semiconductor material layer, which is a nanowire, the outer electric layer wraps around the inner electric layer, thus the first gate dielectric layer is between the first semiconductor material layer and the second gate dielectric layer to separate the first semiconductor material layer from the second gate dielectric layer); and
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a cap layer (Fig. 2, element 150), wherein:
a first portion of the cap layer overlying the first semiconductor material layer is in contact with the second gate dielectric layer (Fig. 2, first portion 150/left of the cap layer overlying the first semiconductor material layer 120/left is in contact with the dielectric stack 110, thus in contact with the second gate dielectric layer), and
a second portion of the cap layer overlying the second semiconductor material layer is in contact with the first gate dielectric layer (Fig. 2, a second portion 150/right of the cap layer overlying the second semiconductor material layer 120/right is in contact with the dielectric stack 110, thus in contact with the first gate dielectric layer).
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Regarding to claim 18, Song teaches
a first gate electrode underlying the first portion of the cap layer and surrounding the first semiconductor material layer (Fig. 2), and
a second gate electrode underlying the second portion of the cap layer and surrounding the second semiconductor material layer (Fig. 2).
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Regarding to claim 19, Song teaches
a third semiconductor material layer extending between the first source/drain region and the second source/drain region (Fig. 2, there are three wires shown in the left stack, the third semiconductor material layer is the second wire from the top); and
an end spacer disposed between the first semiconductor material layer and the third semiconductor material layer (Fig. 1, the spacer between the source/drain and the gate electrodes).
Regarding to claim 20, Song teaches a third semiconductor material layer extending between the third source/drain region and the fourth source/drain region (Fig. 2, there are three wires shown in the right stack, the third semiconductor material layer is the second wire from the top), wherein the second gate dielectric layer is between the second semiconductor material layer and the third semiconductor material layer (Fig. 2).
Allowable Subject Matter
Claims 1-11 are allowed. The following is an examiner’s statement of reasons for allowance of claims 1-11.
Regarding to claim 1, the prior art fails to anticipate or render obvious the claimed limitations including “a sidewall spacer is separated from the cap layer by the second gate dielectric layer in a direction parallel to a top surface of the first gate electrode” in combination with the rest of limitations recited in claim 1.
Comparing to the prior-art of the record, the most relevant prior art is Song et al. (U.S. Patent No. 10,128,379). Song discloses the claimed limitations except for the limitations listed above.
Song discloses a semiconductor arrangement, comprising:
a semiconductor material layer extending between a first source/drain region and a second source/drain region (Figs. 1-2, column 3, lines 19-20, first semiconductor material layer 120/left extending between first source/drain region and second source/drain region);
a first gate dielectric layer comprising a first high-k dielectric material and surrounding the semiconductor material layer (Figs. 1-2; column 5, lines 56-60; column 6, lines 5-8, inner dielectric layer of stack layer 110);
a second gate dielectric layer comprising a second dielectric material different than the first high-k dielectric material and surrounding the first gate dielectric layer (Figs. 1-2; column 5, lines 56-60; column 6, lines 5-8, outer dielectric layer of stack layer 110),
wherein the first gate dielectric layer is between the semiconductor material layer and the second gate dielectric layer to separate the semiconductor material layer from the second gate dielectric layer (the inner electric layer wraps around the first semiconductor material layer, which is a nanowire, the outer electric layer wraps around the inner electric layer, thus the first gate dielectric layer is between the first semiconductor material layer and the second gate dielectric layer to separate the first semiconductor material layer from the second gate dielectric layer);
a first gate electrode surrounding the second gate dielectric layer, the first gate dielectric layer, and the semiconductor material layer (Figs. 1-2, first gate electrode 130/left surrounding the first semiconductor material layer 120/left and in contact with the second gate dielectric layer); and
a cap layer over the first gate electrode (Fig. 2, element 150).
Claims 2-11 are dependent from claim 1 thus they are allowable for the same reasons with claim 1.
Pertinent Art
For the benefits of the Applicant, US-20170154958-A1, US-20190115443-A1, US-10734286-B1, US-10998234-B2, US-10074575-B1, US-9997519-B1, US-10957601-B2, and US-10700064-B1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to discloses a sidewall spacer is separated from the cap layer by the second gate dielectric layer in a direction parallel to a top surface of the first gate electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Vu A Vu whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VU A VU/Primary Examiner, Art Unit 2897
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