DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12,142,676 (hereinafter Patent’676) in view of US 2022/0376082 to Zhang et al. (hereinafter Zhang).
Claim 7 of Patent’676 recites a method for forming a high electron mobility transistor (Col. 10, lines 31-32), comprising:
forming an epitaxial stack on a substrate (Col. 10, line 33);
forming a gate structure on the epitaxial stack (Col. 10, lines 34-39), wherein the gate structure comprises:
a semiconductor gate layer;
a metal gate layer on the semiconductor gate layer; and
a spacer on a top surface of the semiconductor gate layer and a sidewall of the metal gate layer;
forming a passivation layer covering the epitaxial stack and the gate structure (Col. 10, lines 40-42);
forming an opening through the passivation layer on the gate structure to expose a portion of the space (Col. 10, lines 43-45); and
removing the spacer through the opening to form an air gap between the gate structure and the passivation layer (Col. 10, lines 46-48).
Further, claim 7 of Patent’676 does not specifically recite removing the spacer to form an air gap between the sidewall of metal gate layer, the top surface of the semiconductor gate layer and a sidewall of the passivation layer.
However, Zhang teaches forming the spacer (141/143) (Zhang, Figs. 2A, 5A-5B, ¶0028-¶0029, ¶0040-¶0044, ¶0076-¶0079) on a top surface of the semiconductor gate layer (180) and a sidewall of the metal gate layer (120), such that the spacer (141/143) is between the sidewall of metal gate layer (120), the top surface of the semiconductor gate layer (180) and a sidewall of the passivation layer (150/190).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify claim 7 of Patent’676 by forming the spacer on a top surface of the semiconductor gate layer and a sidewall of the metal gate layer as taught by Zhang, wherein the spacer is removed to form an air gap to have the method, comprising: removing the spacer to form an air gap between the sidewall of metal gate layer, the top surface of the semiconductor gate layer and a sidewall of the passivation layer, in order to prevent parasitic resistance between the drain electrode and the gate structure to improve performance of the semiconductor enhancement-mode device (Zhang, ¶0003, ¶0034, ¶0035, ¶0042).
Claim Objections
Claims 3 and 4 are objected to because of the following informalities:
Claim 3 recites “filling the opening the gate structure” which should be replaced with “filling the opening on the gate structure”, to improve claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0376082 to Zhang in view of Naoki Sakura (JP H11274175 A, cited in IDS of 10/15/2024, hereinafter Sakura).
With respect to claim 1, Zhang discloses a method for forming a high electron mobility transistor (Zhang, Figs. 2A, 5A-5B, ¶0019-¶0044, ¶0076-¶0080), comprising:
forming an epitaxial stack (105/111/113) (Zhang, Figs. 2A, 5A-5B, ¶0040, ¶0077) on a substrate (100);
forming a gate structure (120/180/141/143) (Zhang, Figs. 2A, 5A-5B, 3I-3K, ¶0040-¶0044, ¶0063-¶0065, ¶0078-¶0079) on the epitaxial stack (105/111/113), wherein the gate structure (120/180/141/143) comprises:
a semiconductor gate layer (180) (Zhang, Figs. 2A, 5A-5B, ¶0040-¶0044);
a metal gate layer (120) (Zhang, Figs. 2A, 5A-5B, 3I-3K, ¶0027, ¶0040-¶0044, ¶0063-¶0065) on the semiconductor gate layer (180); and
a spacer (141/143) (Zhang, Figs. 2A, 5A-5B, ¶0028-¶0029, ¶0040-¶0044, ¶0076-¶0079) on a top surface of the semiconductor gate layer (180) and a sidewall of the metal gate layer (120);
forming a passivation layer (150/190) (Zhang, Figs. 2A, 5A-5B, 3L, ¶0033, ¶0062, ¶0066, ¶0076-¶0079) covering the epitaxial stack (105/111/113) and the gate structure (120/180/141/143);
forming an opening (820) (Zhang, Figs. 2A, 5A-5B, 3M, ¶0067, ¶0076-¶0079) through the passivation layer (190) on the gate structure (120/180/141/143).
Further, Zhang does not specifically disclose the method, comprising: forming an opening to expose a portion of the spacer; and removing the spacer through the opening to form an air gap between the sidewall of metal gate layer, the top surface of the semiconductor gate layer and a sidewall of the passivation layer.
However, Sakura teaches forming a FET transistor (Sakura, Figs. 2(A)-2(E), pp. 2-6) comprising forming an opening (14) (Sakura, Figs. 2C-2D, pp. 3-4) on the gate structure (3) and through the passivation layer (13) to expose the insulating spacer layer (9/10); and removing a portion of the insulating spacer layer (9/10) (Sakura, Fig. 2D, pp. 3-4) through the opening (14) to form an air gap (e.g., the space 7/8 filled with gas and has a dielectric constant of about 1) between the sidewall of the gate structure (3) and a sidewall of the passivation layer (13).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang by forming an air gap between the sidewall of the gate structure and a sidewall of the passivation layer by removing the spacer layer as taught by Sakura, wherein removing the spacer layer exposes a top surface of the semiconductor gate layer of Zhang to have the method for forming a high electron mobility transistor, comprising: forming an opening to expose a portion of the spacer; and removing the spacer through the opening to form an air gap between the sidewall of metal gate layer, the top surface of the semiconductor gate layer and a sidewall of the passivation layer, in order to provide an air gap to reduce parasitic capacitance between the gate electrode and the substrate, and the gate electrode and the source electrode and the drain electrode to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
Regarding claim 2, Zhang in view of Sakura discloses the method for forming a high electron mobility transistor of claim 1. Further, Zhang does not specifically disclose the method, wherein the air gap continuously surrounds the metal gate layer in a top view.
However, Sakura teaches forming an air gap (7/8) (Sakura, Figs. 1, 2D, pp. 3-4) on sidewalls of the gate layer (3) in a top view, to provide an air gap to reduce parasitic capacitance between the gate electrode and the substrate, and the gate electrode and the source electrode and the drain electrode to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura by forming the air gap of Sakura on the sidewall of the gate structure such that the air gap completely surrounds the gate layer in a top view to have the method for forming a high electron mobility transistor, wherein the air gap continuously surrounds the metal gate layer in a top view, in order to further reduce parasitic capacitance between the gate electrode and the substrate to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
Regarding claim 9, Zhang in view of Sakura discloses the method for forming a high electron mobility transistor of claim 1. Further, Zhang does not specifically disclose the method, wherein a width of the opening is larger than a width of the metal gate layer.
However, Sakura teaches forming the opening (14) (Sakura, Figs. 2C-2D, pp. 3-4) on the gate structure (3) and through the passivation layer (13) to expose the insulating spacer layer (9/10), wherein a width of the opening (14) is larger than a width of a lower portion (3a) of the gate layer (3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura by forming an air gap between the sidewall of the gate structure and a sidewall of the passivation layer by removing the spacer layer as taught by Sakura, wherein the gate layer includes a lower portion having smaller width than a width of the opening on the gate layer to have the method for forming a high electron mobility transistor, wherein a width of the opening is larger than a width of the metal gate layer, in order to provide an air gap to reduce parasitic capacitance between the gate electrode and the substrate, and the gate electrode and the source electrode and the drain electrode to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
Regarding claim 10, Zhang in view of Sakura discloses the method for forming a high electron mobility transistor of claim 1. Further, Zhang does not specifically disclose the method, wherein the sidewall of the passivation layer is concurrently in direct contact with the air gap and a sidewall of the semiconductor gate layer.
However, Sakura teaches forming an air gap (7/8) (Sakura, Fig. 2D, pp. 3-4) on sidewalls of the gate layer (3), wherein the sidewall of the passivation layer (13) is concurrently in direct contact with the air gap (7/8) and a sidewall of the gate layer (3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura by forming an air gap between the sidewall of the gate structure and a sidewall of the passivation layer by removing the spacer layer as taught by Sakura, wherein the gate layer includes the semiconductor gate layer of Zhang to have the method for forming a high electron mobility transistor, wherein the sidewall of the passivation layer is concurrently in direct contact with the air gap and a sidewall of the semiconductor gate layer, in order to provide an air gap to reduce parasitic capacitance between the gate electrode and the substrate, and the gate electrode and the source electrode and the drain electrode to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0376082 to Zhang in view of Sakura (JP H11274175) as applied to claim 1, and further in view of Makiyama et al. (US 2004/0058485, cited in IDS of 10/15/2024, hereinafter Makiyama).
Regarding claim 2, Zhang in view of Sakura discloses the method for forming a high electron mobility transistor of claim 1. Further, Zhang does not specifically disclose the method, wherein the air gap continuously surrounds the metal gate layer in a top view.
However, Makiyama teaches a method for forming a high electron mobility transistor (Makiyama, Figs. 1A-1H, ¶0003, ¶0006, ¶0014-¶0015, ¶0028-¶0046) that comprises forming an air gap (e.g., hollow space H with dielectric constant 1) by removing a spacer layer (F) (Makiyama, Figs. 1B-1DX, 1FP, ¶0033-¶0038, ¶0041-¶0044) completely surrounding the gate structure in in a top view, to reduce parasitic capacitance of the gate electrode, and thus to obtain a reliable semiconductor device (Makiyama, ¶0013-¶0015, ¶0044-¶0046).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura by forming the air gap completely surrounding the gate layer in a top view as taught by Makiyama to have the method for forming a high electron mobility transistor, wherein the air gap continuously surrounds the metal gate layer in a top view, in order to reduce parasitic capacitance of the gate electrode, and thus to obtain a reliable semiconductor device (Makiyama, ¶0013-¶0015, ¶0044-¶0046).
Regarding claim 3, Zhang in view of Sakura discloses the method for forming a high electron mobility transistor of claim 1. Further, Zhang discloses the method, further comprising forming a gate electrode (e.g., an upper portion of gate electrode 120) (Zhang, Figs. 2A, 3O, ¶0069, ¶0076-¶0079) on the passivation layer (150/190), but does not specifically disclose the method, further comprising filling the opening on the gate structure and sealing the air gap.
However, Makiyama teaches a method for forming a high electron mobility transistor (Makiyama, Figs. 1A-1H, ¶0003, ¶0006, ¶0014-¶0015, ¶0028-¶0046) that comprises removing a portion of the insulating layer (F) (Makiyama, Fig. 1G, ¶0043-¶0044) through the opening (39) to form an air gap (e.g., hollow space H with dielectric constant 1) between the gate structure (G) and the passivation layer (IL), and forming a gate electrode (41/43) (Makiyama, Fig. 1H, ¶0045-¶0046) on the passivation layer (IL) and the gate structure (G) to seal the air gap (e.g., the hollow space H).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura by forming HEMT device comprising a hollow space surrounding the gate electrode and sealing the hollow space as taught by Makiyama to have the method for forming a high electron mobility transistor, further comprising filling the opening on the gate structure and sealing the air gap, in order to reduce parasitic capacitance of the gate electrode, and thus to obtain a reliable semiconductor device (Makiyama, ¶0013-¶0015, ¶0044-¶0046).
Regarding claim 4, Zhang in view of Sakura and Makiyama discloses the method for forming a high electron mobility transistor of claim 3. Further, Zhang discloses the method, wherein the spacer (141/143) (Zhang, Fig. 2A, ¶0028-¶0029, ¶0040-¶0044, ¶0076-¶00790 is above the top surface of the semiconductor gate layer (180) and below a top surface of the metal gate layer (120), but does not specifically disclose the method, wherein the air gap is above the top surface of the semiconductor gate layer and below a top surface of the metal gate layer.
However, Sakura teaches forming an air gap (7/8) (Sakura, Figs. 1, 2D, pp. 3-4) on sidewalls of the gate layer (3) by removing the spacer layer (9/10), to provide an air gap to reduce parasitic capacitance between the gate electrode and the substrate, and the gate electrode and the source electrode and the drain electrode to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura/Makiyama by removing the spacer layer of Zhang to form the air gap as taught by Sakura to have the method for forming a high electron mobility transistor, wherein the air gap is above the top surface of the semiconductor gate layer and below a top surface of the metal gate layer, in order to reduce parasitic capacitance between the gate electrode and the substrate to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0376082 to Zhang in view of Sakura (JP H11274175) as applied to claim 1, and further in view of Constant et al. (US 2022/0254894, cited in IDS of 10/15/2024, hereinafter Constant).
Regarding claim 5, Zhang in view of Sakura discloses the method for forming a high electron mobility transistor of claim 1. Further, Zhang discloses the method, wherein the passivation layer (150/190) (Zhang, Figs. 2A, 5A-5B, 3L, ¶0033, ¶0062, ¶0066, ¶0076-¶0079) comprises a first layer (150) covering the epitaxial stack (105/111/113) and the gate structure (120/180/141/143) and a second layer (190) on the first layer (150), wherein the spacer (141/143), the first layer (150) and the second layer (190) are made of different materials (Zhang, Figs. 2A, 5A-5B, 3L, ¶0033) having etching selectivity, but does not specifically disclose the method, wherein a first layer conformally and continuously covering the epitaxial stack and the gate structure.
However, Constant teaches forming a HEMT transistor comprising an epitaxial stack (124/126/128) (Constant, Figs. 1-7, ¶0030, ¶0034-¶0040, ¶0064) formed on a substrate (e.g., 122) by a metalorganic chemical vapor deposition (MOCVD), and a passivation layer (708) (Constant, Figs. 1-7, ¶0064) formed to cover the epitaxial stack (124/126/128) conformally and continuously by atomic layer deposition, to reduce dangling bonds of the underlying semiconductor layer, to provide improved HEMT transistor having a high quality channel material to maintain 2DEG channel and to obtain improved value for on-state resistance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura by forming a passivation layer on the epitaxial stack and the gate electrode as taught by Constant to have the method, wherein a first layer conformally and continuously covering the epitaxial stack and the gate structure, in order to provide improved HEMT transistor having a high quality channel material to maintain 2DEG channel and to obtain improved value for on-state resistance (Constant, ¶0001, ¶0005, ¶0030, ¶0038, ¶0040).
Regarding claim 6, Zhang in view of Sakura and Constant discloses the method for forming a high electron mobility transistor of claim 5. Further, Zhang discloses the method, wherein the spacer (141/143) (Zhang, Figs. 2A, 5B, ¶0030) is made of silicon nitride (SiN), the first layer (150) is made of aluminum oxide (Zhang, Figs. 2A, 5B, ¶0033), and the second layer (190) is made of silicon oxide, but does not specifically disclose that the first layer is made of Al2O3, and the second layer is made of SiO2.
However, Zhang teaches forming the first layer (150) (Zhang, Figs. 2A, 5B, ¶0033) and the second layer (190) made of different materials including silicon oxide, and aluminum oxide. Further, Constant teaches forming the first passivation layer (708) (Constant, Figs. 1-7, ¶0064) made of Al2O3, to reduce dangling bonds of the underlying semiconductor layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura/Constant by forming the first passivation layer and the second passivation layer made of different oxide materials as taught by Zhang, wherein the first passivation layer made of Al2O3 as taught by Constant to have the method, wherein the first layer is made of Al2O3, and the second layer is made of SiO2, in order to reduce dangling bonds of the underlying semiconductor layer, and to provide improved HEMT transistor having a high quality channel material to maintain 2DEG channel and to obtain improved value for on-state resistance (Constant, ¶0001, ¶0005, ¶0030, ¶0038, ¶0040).
Regarding claim 7, Zhang in view of Sakura and Constant discloses the method for forming a high electron mobility transistor according to claim 5. Further, Zhang does not specifically disclose the method, wherein the air gap and the semiconductor gate layer are spaced from the second layer by the first layer.
However, Sakura teaches forming a semiconductor device (Sakura, Figs. 3(A)-3(E), pp. 2-4), wherein regardless of the shape of a gate electrode structure, wiring, and the like, a space is formed around the gate electrode structure to greatly reduce parasitic capacitance between the gate electrode and the substrate and the gate electrode and the source electrode and the drain electrode to improve performance in a high frequency band. Specifically, Sakura teaches a method comprising forming an insulating layer (e.g., an insulating layer 16 formed on the substrate and lower portion of the gate 3, and an insulating layer 10 formed on the substrate and the gate 3; note that the limitation “an insulating layer” is interpreted as “one or more” because the claim uses an open-ended transition phrase “comprising”) (Sakura, Fig. 3(A), p. 4) covering the substrate (2/1) and the gate structure (3); forming the second passivation layer (13) (Sakura, Fig. 3(C), p. 4) on the first insulating layer (16/10); and forming the opening (14) (Sakura, Fig. 3(D), p. 4) through the second passivation layer (13) and the insulating layer (e.g., 10) to expose the portion of the spacer (9), wherein the air gap (e.g., 8) (Sakura, Fig. 3(E), p. 4) and the gate structure (3) are spaced from the second passivation layer (13) by the first insulating layer (16) that is formed to protect a surface of the substrate in the gap (7/8) (Sakura, Fig. 3(E), p. 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura/Constant by forming the first layer on a surface of the substrate and the second passivation layer on the first layer as taught by Sakura to have the method, wherein the air gap and the semiconductor gate layer are spaced from the second layer by the first layer, in order to protect a surface of the substrate in the air gap formed to reduce parasitic capacitance between the gate electrode and the substrate, and the gate electrode and the source electrode and the drain electrode to improve performance of the semiconductor device in a high frequency band (Sakura, Abstract, pp. 2-3 and 5).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0376082 to Zhang in view of Sakura (JP H11274175) and Constant (US 2022/0254894) as applied to claim 5, and further in view of Makiyama (US 2004/0058485).
Regarding claim 8, Zhang in view of Sakura and Constant discloses the method for forming a high electron mobility transistor of claim 5. Further, Zhang does not specifically disclose the method, wherein in a top view, the air gap continuously surrounds the metal gate layer, and the first layer continuously surrounds the air gap.
However, Makiyama teaches a method for forming a high electron mobility transistor (Makiyama, Figs. 1A-1H, ¶0003, ¶0006, ¶0014-¶0015, ¶0028-¶0046) that comprises forming an air gap (e.g., hollow space H with dielectric constant 1) by removing a spacer layer (F) (Makiyama, Figs. 1B-1DX, 1FP, ¶0033-¶0038, ¶0041-¶0044) completely surrounding the gate structure in in a top view, and the passivation layer (IL) (Makiyama, Figs. 1E-1EX, ¶0039-¶0040) completely surrounding the spacer layer (F), to reduce parasitic capacitance of the gate electrode, and thus to obtain a reliable semiconductor device (Makiyama, ¶0013-¶0015, ¶0044-¶0046).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming a high electron mobility transistor of Zhang/Sakura/Constant by forming the spacer layer completely surrounding the gate layer, and the passivation layer completely surrounding the spacer layer in a top view as taught by Makiyama, wherein the air gap is formed by removing the spacer layer, and the passivation layer includes the first layer to have the method for forming a high electron mobility transistor, wherein in a top view, the air gap continuously surrounds the metal gate layer, and the first layer continuously surrounds the air gap, in order to provide hollow space surrounding the gate structure to reduce parasitic capacitance of the gate electrode, and thus to obtain a reliable semiconductor device (Makiyama, ¶0013-¶0015, ¶0044-¶0046).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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