Prosecution Insights
Last updated: October 23, 2026
Application No. 18/915,389

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
Oct 15, 2024
Priority
Jun 16, 2020 — CN 202010546950.X +2 more
Examiner
MILLER, JAMI VALENTINE
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1050 granted / 1106 resolved
+26.9% vs TC avg
Minimal +4% lift
Without
With
+3.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
34 currently pending
Career history
1130
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
31.1%
-8.9% vs TC avg
§102
41.8%
+1.8% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1106 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-7 are pending in this application. Foreign Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in parent Application No. 16/927918, filed on 7/13/2020. Information Disclosure Statement Acknowledgment is made that the information disclosure statement has been received and considered by the examiner. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same. Drawings There are no objections or rejections to the drawings. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Gill et al. (US Patent Application Pub. No 2007/0064350) hereinafter referred to as Gill. Per Claim 1 Gill discloses a semiconductor device (see fig. 5), comprising a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises: a pinned layer (506) on the substrate; The examiner notes that the term "on" includes "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween) a reference layer (507/508) on the pinned layer; a barrier layer (510) on the reference layer; and a free layer (512) on the barrier layer, wherein the free layer and the barrier layer comprises same width (as shown in figure 5) and the barrier layer and the reference layer comprise different widths (as shown in figure 5). Per Claim 2 Gill discloses the device of claim 1 (see fig. 5), including where a width of the free layer (512) is less than a width of the pinned layer (506). (as shown in figure 5) Per Claim 3 Gill discloses the device of claim 1 (see fig. 5), including where a width of the free layer (512) is less than a width of the reference layer (507/508). (as shown in figure 5) Per Claim 4 Gill discloses the device of claim 1 (see fig. 5), including where the free layer (512) and the reference layer (507/508) comprise same material. (CoFe, see figure 5) Claims 1-3 and 5-7 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Hosotani et al. (US Patent Application Pub. No 2010/0020592) hereinafter referred to as Hosotani. Per Claim 1 Hosotani discloses a semiconductor device (see fig. 4C-D), comprising a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises: a pinned layer (14) on the substrate; a reference layer (15) on the pinned layer; a barrier layer (18) on the reference layer; and a free layer (20) on the barrier layer, wherein the free layer and the barrier layer comprises same width (as shown in figure 4C) and the barrier layer and the reference layer comprise different widths (as shown in figure 4C). Per Claim 2 Gill discloses the device of claim 1 (see fig. 4C), including where a width of the free layer (20) is less than a width of the pinned layer (14). (as shown in figure 4C) Per Claim 3 Gill discloses the device of claim 1 (see fig. 4C), including where a width of the free layer (20) is less than a width of the reference layer (15). (as shown in figure 4C) Per Claim 5 Gill discloses the device of claim 1 (see fig. 4C-D), including a spacer (24) adjacent to the barrier layer (18) and the free layer (20); and a cap layer (21) adjacent to the spacer (24) and the pinned layer (14). The examiner notes that the term "adjacent" includes "directly adjacent" (no intermediate materials, elements or space disposed therebetween) and "indirectly adjacent" (intermediate materials, elements or space disposed therebetween). Per Claim 6 Gill discloses the device of claim 5 (see fig. 4C), including a top electrode (22) on the free layer (20), wherein a top surface of the spacer (24) is even with a top surface of the top electrode (22). Per Claim 7 Gill discloses the device of claim 5 (see fig. 4C), including where the spacer ((24) may be SiN [0081]) and the cap ((21) may be Ta or Ru [0077]) layer comprise different materials. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith. Glova (US 10,199,433 is provided as an analogous reference teaching many of the features of claim 1. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jami Valentine Miller/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Oct 15, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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FE-X TEMPLATING LAYERS FOR GROWTH OF PERPENDICULARLY MAGNETIZED HEUSLER FILMS ON TOP OF A TUNNEL BARRIER
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+3.9%)
1y 12m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1106 resolved cases by this examiner. Grant probability derived from career allowance rate.

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