DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12148826 in view of Chen et al. (US20210313181A1).
Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 1:
A lateral diffused metal oxide semiconductor (LDMOS) device, comprising:
Claim 1:
A lateral diffused metal oxide semiconductor (LDMOS) device, comprising
a first fin-shaped structure on a substrate; a second fin-shaped structure adjacent to the first fin-shaped structure;
a first fin-shaped structure on a substrate; a second fin-shaped structure adjacent to the first fin-shaped structure,
a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure;
a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure;
a first gate structure on the first fin-shaped structure and part of the STI;
a first gate structure on the first fin-shaped structure;
a second gate structure on the second fin-shaped structure; and
a second gate structure on the second fin-shaped structure; and
an air gap between the first gate structure and the second gate structure.
an air gap between the first gate structure and the second gate structure and directly on the STI.
Claim 2; The LDMOS device of claim 1, further comprising:
Claim 2: The LDMOS device of claim 1, further comprising:
a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; a first contact plug on the source region; and a second contact plug on the drain region.
an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and a first contact plug on the source region and a second contact plug on the drain region.
Claim 3; The LDMOS device of claim 2, wherein the air gap is in the ILD layer.
Claim 3: The LDMOS device of claim 2, wherein the air gap is in the ILD layer.
Claim 4: The LDMOS device of claim 1, wherein a width of the second gate structure is less than a width of the first gate structure.
Claim 4: The LDMOS device of claim 1, wherein a width of the second gate structure is less than a width of the first gate structure.
Claim 5: The LDMOS device of claim 1, wherein the air gap is directly on the STI.
Claim 1: an air gap between the first gate structure and the second gate structure and directly on the STI.
Claim 6: The LDMOS device of claim 1, wherein the first gate structure and the second gate structure comprise metal gates.
Claim 6: The LDMOS device of claim 1, wherein the first gate structure and the second gate structure comprise metal gates.
Regarding claim 1, claim 1 of Lin teaches a lateral diffused metal oxide semiconductor (LDMOS) device, comprising: a first fin-shaped structure on a substrate; a second fin-shaped structure adjacent to the first fin-shaped structure; a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure; a first gate structure on the first fin-shaped structure and part of the STI; a second gate structure on the second fin-shaped structure; and an air gap between the first gate structure and the second gate structure.
However, claim 1 of Lin does not teach wherein a first gate structure is part of the STI.
Fig.30A of Chen teaches wherein gate stack 60 is part of isolation region 22.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have gate stack being part of the isolation region, as taught by Chen, because the isolation region provides isolation while allowing gate to control signal.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 6 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chen et al. (US20210313181A1).
Regarding claim 1, Fig.30A of Chen teaches a lateral diffused metal oxide semiconductor (LDMOS) device, comprising:
a first fin-shaped structure 24 (para.0009) on a substrate 20 (para.0009);
a second fin-shaped structure 24 (para.0009, second fin being located on the right side of dielectric region 82) adjacent to the first fin-shaped structure 24;
a shallow trench isolation (STI) 22 (para.0053) between the first fin-shaped structure 24 and the second fin-shaped structure 24;
a first gate structure 60 (para.0041, first gate structure being the one on the left side of the dielectric region 82) on the first fin-shaped structure 24 and part of the STI 22;
a second gate structure 60 (para.0041, first gate structure being the one on the right side of the dielectric region 82) on the second fin-shaped structure 24; and
an air gap 84 (para.0057) between the first gate structure 24 (first gate structure being the one on the left side of the dielectric region 82) and the second gate structure 24 (first gate structure being the one on the right side of the dielectric region 82).
Regarding claim 2, Fig.16 of Chen teaches the LDMOS device of claim 1, further comprising: a source region 42 (para.0010) adjacent to one side of the first gate structure 30 (para.0010) on the first fin-shaped structure 24 (para.0010); a drain region 42 (para.0010, on the right) adjacent to one side of the second gate structure 30 (para.0010) on the second fin-shaped structure 24 (para.0010); an interlayer dielectric (ILD) layer 48 (para.0039) around the first gate structure 30 and the second gate structure 30; a first contact plug 112 (Fig.30C, para.0064) on the source region 42; and a second contact plug 112 (Fig.30C, para.0064) on the drain region 42.
Regarding claim 3, Fig.30A of Chen teaches the LDMOS device of claim 2, wherein the air gap 84 (para.0057) is in the ILD layer 48/82 (para.0057).
Regarding claim 6, Fig.30A of Chen teaches the LDMOS device of claim 1, wherein the first gate structure 60 (para.0042, wherein the gate electrodes 56 may include a metal-containing material) and the second gate structure comprise metal gates 60 (para.0042, wherein the gate electrodes 56 may include a metal-containing material).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20210313181A1) in view of Wang et al. (US9853021B1).
Regarding claim 4, Chen does not teach wherein a width of the second gate structure is less than a width of the first gate structure.
Fig.8 of Wang teaches wherein a width of gate structure 28 is less than a width of gate structure 24.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Wang’s gate structure 28, with a width that is less than a width of gate structure 24, in the teachings of Chen because the left portion 32 and right portion 34 of the gate structure 24 sitting on both the first fin-shaped structure 14 and the STI 22 preferably includes different work function values thereby achieving different threshold voltage (Wang, [col.4, lines 1-5]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20210313181A1) in view of Chang et al. (US20170229452A1).
Regarding claim 5, Chen does not teach wherein the air gap is directly on the STI.
Chang teaches a fin field effect transistor (FinFET) that includes a trench 206 (Fig.2B, para.0015) between the first semiconductor fin 208a and the second semiconductor fin 208b. The insulator is disposed in the trench 206; and a first dielectric layer that includes an air gap 219 (para.0024) is disposed on the insulator (para.0034).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Chang’s air gap in the teachings of Chen in order to prevent parasitic capacitance formed between the first gate and the second gate (Chang, [para.0032]).
Conclusion
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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