DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 12,148,809. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-12 of U.S. Patent No. 12,148,809 disclose all limitations of claims 1-12 of the instant application, although claims 1-12 of U.S. Patent No. 12,148,809 draw to a structure and claims 1-12 of the instant application draw to a method forming a structure. The method steps are not claimed to impart to a specific order. Every element cited in claims 1-12 of U.S. Patent No. 12,148,809 needs a method step to form.
18/916,723
U.S. Patent No. 12,148,809
1 A method for forming a layout pattern of a static random access memory (SRAM), comprising:
forming a plurality of fin structures located on a substrate;
forming a plurality of gate structures located on the substrate, wherein the plurality of gate structures span the plurality of fin structures, to form a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor),a PG2A(third access transistor) and a PG2B (fourth access transistor) on the substrate, wherein the PD1A and the PD1B are connected in parallel, and the PD2A and the PD2B are connected in parallel;
wherein the plurality of gate structures include a first J-shaped gate structure, the first J-shaped gate structure spans a part of the fin structures and forms the PU1, the PD1A and the PD1B, the first J-shaped gate structure comprises a long side structure, a short side structure and a connection structure, and the first J-shaped gate structure is an integrally formed structure.
2. The method for forming a layout pattern of SRAM according to claim 1, wherein the long side structure and the short side structure are arranged along a first direction, and the connection structure and each fin structure are arranged along a second direction.
3. The method for forming a layout pattern of SRAM according to claim 1, wherein the short side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PD1B.
4. The method for forming a layout pattern of SRAM according to claim 1, wherein the long side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PU1 and the PD1A.
5. The method for forming a layout pattern of SRAM according to claim 2, further comprising forming a second gate structure arranged along the first direction, and the second gate structure spans a part of the fin structures and constitutes the PG1A.
6. The method for forming a layout pattern of SRAM according to claim 5, wherein the second gate structure and the short side structure are aligned with each other in the first direction.
7. The method for forming a layout pattern of SRAM according to claim 6, further comprising forming a third gate structure arranged along the first direction, and the third gate structure spans a part of the fin structures and constitutes the PG1B.
8. The method for forming a layout pattern of SRAM according to claim 7, wherein the third gate structure and the long side structure are aligned with each other in the first direction.
9. The method for forming a layout pattern of SRAM according to claim 8, further comprising forming a first local interconnection layer and a second local interconnection layer, wherein the first local interconnection layer is located between the second gate structure and the third gate structure.
10. The method for forming a layout pattern of SRAM according to claim 9, wherein the second local interconnection layer is located between the long side structure and the short side structure.
11. The method for forming a layout pattern of SRAM according to claim 10, wherein the connection structure is located between the first local interconnection layer and the second local interconnection layer.
12. The method for forming a layout pattern of SRAM according to claim 9, further comprising forming a metal wire electrically connecting the first local interconnection layer and the second local interconnection layer, wherein the metal wire and the connection structure are located in different layers.
1. A layout pattern of a static random access memory (SRAM), comprising:
a plurality of fin structures located on a substrate;
a plurality of gate structures located on the substrate, wherein the plurality of gate structures span the plurality of fin structures, to form a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD 1A (first pull-down transistor), a PD 1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PGIA (first access transistor), a PGIB (second access transistor),a PG2A(third access transistor) and a PG2B (fourth access transistor) on the substrate, wherein the PD1A and the PD1B are connected in parallel, and the PD2A and the PD2B are connected in parallel;
wherein the plurality of gate structures
include a first J-shaped gate structure, the first J-shaped gate structure spans a part of the fin structures and forms the PU l, the PD1A and the PD 1B, the first J-shaped gate structure comprises a long side structure, a short side structure and a connection structure, and the first J-shaped gate structure is an integrally formed structure; and
a third gate structure disposed beside the long side structure of the first J-shaped gate structure, and the third gate structure spans a part of the fin structures and constitutes the PG1B, wherein the connection structure of the first J-shaped gate structure is disposed between the third gate structure and the short side structure of the first J-shaped gate structure.
2. The layout pattern of SRAM according to claim 1, wherein the long side structure and the short side structure are arranged along a first direction, and the connection structure and each fin structure are arranged along a second direction.
3. The layout pattern of SRAM according to claim 1, wherein the short side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PD1B.
4. The layout pattern of SRAM according to claim 1, wherein the long side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PU1 and the PD1A.
5. The layout pattern of SRAM according to claim 2, further comprising a second gate structure arranged along the first direction, and the second gate structure spans a part of the fin structures and constitutes the PG 1A.
6. The layout pattern of SRAM according to claim 5, wherein the second gate structure and the short side structure are aligned with each other in the first direction.
This limitation is in claim 1 above
8. The layout pattern of SRAM according to claim 6, wherein the third gate structure and the long side structure are aligned with each other in the first direction.
9. The layout pattern of SRAM according to claim 8, further comprising a first local interconnection layer and a second local interconnection layer, wherein the first local interconnection layer is located between the second gate structure and the third gate structure.
10. The layout pattern of SRAM according to claim 9, wherein the second local interconnection layer is located between the long side structure and the short side structure.
11. The layout pattern of SRAM according to claim 10, wherein the connection structure is located between the first local interconnection layer and the second local interconnection layer.
12. The layout pattern of SRAM according to claim 9, further comprising a metal wire electrically connecting the first local interconnection layer and the second local interconnection layer, wherein the metal wire and the connection structure are located in different layers.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh et al. (U.S. Patent No. 10,529,723, previous published US 2017/0323894).
Regarding to claim 1, Yeh teaches method for forming a layout pattern of a static random access memory (SRAM), comprising:
forming a plurality of fin structures located on a substrate (Fig. 6, elements 54);
forming a plurality of gate structures located on the substrate (Fig. 6, column 2, lines 5-7), wherein the plurality of gate structures span the plurality of fin structures, to form a PU1 (first pull-up transistor) (Fig. 6, please see the attached reproduced figure with annotations), a PU2 (second pull-up transistor) (Fig. 6, please see the attached reproduced figure with annotations), a PD1A (first pull-down transistor) (Fig. 6, please see the attached reproduced figure with annotations), a PD1B (second pull-down transistor) (Fig. 6, please see the attached reproduced figure with annotations), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A(third access transistor) and a PG2B (fourth access transistor) on the substrate (Fig. 6, please see the attached reproduced figure with annotations), wherein the PD1A and the PD1B are connected in parallel, and the PD2A and the PD2B are connected in parallel (Fig. 6);
wherein the plurality of gate structures include a first J-shaped gate structure, the first J-shaped gate structure spans a part of the fin structures and forms the PUI, the PDIA and the PDIB, the first J-shaped gate structure comprises a long side structure, a short side structure and a connection structure, and the first J-shaped gate structure is an integrally formed structure (Fig. 6, please see the attached reproduced figure with annotations).
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Regarding to claim 2, Yeh teaches the long side structure and the short side structure are arranged along a first direction, and the connection structure and each fin structure are arranged along a second direction (Fig. 6, the long side structure and the short side structure are arranged horizontally, each fin structures 54 are arranged vertically).
Regarding to claim 3, Yeh teaches the short side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PD1B (Fig. 6).
Regarding to claim 4, Yeh teaches the long side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PUI and the PDIA (Fig. 6).
Regarding to claim 5, Yeh teaches a second gate structure arranged along the first direction, and the second gate structure spans a part of the fin structures and constitutes the PG1A (Fig. 6, please see the attached reproduced figure with annotations).
Regarding to claim 6, Yeh teaches the second gate structure and the short side structure are aligned with each other in the first direction (Fig. 6, please see the attached reproduced figure with annotations).
Regarding to claim 7, Yeh teaches a third gate structure arranged along the first direction, and the third gate structure spans a part of the fin structures and constitutes the PG1B (Fig. 6, please see the attached reproduced figure with annotations).
Regarding to claim 8, Yeh teaches the third gate structure and the long side structure are aligned with each other in the first direction (Fig. 6, please see the attached reproduced figure with annotations).
Regarding to claim 9, Yeh teaches a first local interconnection layer (Fig. 6, element 84A/B) and a second local interconnection layer (Fig. 6, element 72A), wherein the first local interconnection layer is located between the second gate structure and the third gate structure (Fig. 6).
Regarding to claim 10, Yeh teaches the second local interconnection layer is located between the long side structure and the short side structure (Fig. 6).
Regarding to claim 11, Yeh teaches the connection structure is located between the first local interconnection layer and the second local interconnection layer (Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (U.S. Patent No. 10,529,723), as applied to claim 1-2 and 5-9 above, in view of Fujiwara et al. (U.S. Patent No. 2020/0020699).
Regarding to claim 12, Yeh is silent as to a metal wire electrically connecting the first local interconnection layer and the second local interconnection layer, wherein the metal wire and the connection structure are located in different layers. Fujiwara discloses a metal wire electrically connecting a first local interconnection layer and a second local interconnection layer, wherein the metal wire and the connection structure are located in different layers (Fig. 3C, metal wire M0 electrically connecting first local interconnection layer 310a and the second local interconnection layer 310b, wherein the metal wire M0 and the connection structure MD are located in different layers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yeh in view of Fujiwara to configure a metal wire electrically connecting the first local interconnection layer and the second local interconnection layer, wherein the metal wire and the connection structure are located in different layers, in order to reduce parasitic effects.
Pertinent Art
For the benefits of the Applicant, US-11889673-B2, US-9780099-B1, US-10177132-B2, and US-11088151-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. They disclose the claimed features except for a J-shaped gate structure.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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