DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,150,315. Although the claims at issue are not identical, they are not patentably distinct from each other because regarding claim 1, U.S. Patent No. 12,150,315 discloses a layout pattern for magnetoresistive random access memory (MRAM), comprising: a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region; a first gate pattern extending along a first direction from the first active region to the second active region; a second gate pattern extending along the first direction from the first active region to the second active region; a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, wherein the first MTJ comprises a dummy MTJ; a second MTJ between the first gate pattern and the second gate pattern in the first active region, wherein top surfaces of the first MTJ and the second MTJ are coplanar; a first diffusion region and a second diffusion region extending along a second direction and adjacent to the first gate pattern and the second gate pattern in the word line connecting region, wherein the first MTJ is between and not overlapping the first diffusion region and the second diffusion region; and a metal interconnection on a same level as the first MTJ in the word line connecting region, wherein top surfaces of the first top electrode and the metal interconnection are coplanar.
U.S. Patent No. 12,150,315 fails to disclose a first top electrode on the first MTJ. However, it would have been prima facie obvious to one of ordinary skill in the art, or it is inherent that an MTJ stack would have a top electrode. That’s is, a top electrode would have to be in the connecting region cited in the claim, to facilitate the connection with the metal interconnection.
Regarding claim 2, U.S. Patent No. 12,150,315 discloses in claim 2, a layout pattern for MRAM wherein the first direction is orthogonal to the second direction.
Regarding claim 3, U.S. Patent No. 12,150,315 discloses in claim 3, a layout pattern further comprising a third MTJ between the first gate pattern and the second gate pattern in the second active region.
Regarding claim 4, U.S. Patent No. 12,150,315 discloses in claim 4, a layout pattern for MRAM further comprising: a first metal interconnection directly under the second MTJ; a second metal interconnection directly under the third MTJ; a first inter-metal dielectric (IMD) layer around the first MTJ, the second MTJ, and the third MTJ; a second IMD layer around the first metal interconnection and the second metal interconnection; and a stop layer under the second IMD layer.
Regarding claim 5, U.S. Patent No. 12,150,315 discloses in claim 5, a layout pattern for MRAM wherein the second IMD layer is under the first IMD layer.
Regarding claim 6, U.S. Patent No. 12,150,315 discloses in claim 6, a layout pattern for MRAM, wherein a top surface of the second IMD layer comprises a curve.
Regarding claim 7, U.S. Patent No. 12,150,315 discloses in claim 7, a layout pattern for MRAM, wherein bottom surfaces of the stop layer and the first metal interconnection are coplanar.
Regarding claim 8, U.S. Patent No. 12,150,315 discloses in claim 8, a layout pattern for MRAM of claim 1, wherein bottom surfaces of the first MTJ and the second MTJ are coplanar.
Pertinent References
Kajiyama et al., US 2010/0232210 shows in fig.2-20, and discloses a layout pattern for magnetoresistive random access memory (MRAM), comprising: a substrate (11) having a first active region (AA)[0051, 0052], a second active region (AA close to WL1, WL2), and a word line (WL) connecting region between the first active region and the second active region (AA); a first gate pattern (15WL)(portion close to first and second MTJ) extending along a first direction from the first active region to the second active region (AA); a second gate pattern (13) extending along the first direction from the first active region to the second active region (AA)
Liou et al., US 20210098685 shows in fig.1, a second IMD layer (140 or 145) around the first metal interconnection and the second metal interconnection; and a stop layer (143) under the second IMD layer
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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