Prosecution Insights
Last updated: October 22, 2026
Application No. 18/917,587

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SEMICONDUCTOR DEVICE STRUCTURE

Non-Final OA §102§DP
Filed
Oct 16, 2024
Priority
Feb 25, 2021 — continuation of 11/688,767 +1 more
Examiner
SPALLA, DAVID C
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
724 granted / 857 resolved
+16.5% vs TC avg
Minimal +5% lift
Without
With
+4.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
18 currently pending
Career history
886
Total Applications
across all art units

Statute-Specific Performance

§103
52.3%
+12.3% vs TC avg
§102
31.4%
-8.6% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 857 resolved cases

Office Action

§102 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/16/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner, Claim Objections Claim 7 is objected to because of the following informalities: Claim 7 is dependent on Claim 1 but recites “the first interface layer”. The first interface layer is not mentioned until Claim 6. Claim 7 appears to have a typographical error and should instead be a dependent of Claim 6. For purposes of examination, Claim 7 is being treated as a dependent of Claim 6. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2020/0098859 to Reboh et al (hereinafter Reboh). Regarding Claim 1, Reboh discloses a semiconductor device structure, comprising: first nanostructures (116.1, Fig. 12A) formed over a substrate; a first gate structure (136) wrapping around the first nanostructures; a first source/drain epitaxial structure (132) formed beside the first nanostructures; a first inner spacer (126; located proximate to nanostructure 116.1) between the first gate structure and the first source/drain epitaxial structure (132) and having a first sidewall adjacent to the first gate structure (136, Fig. 12A); second nanostructures (116.2) formed over the first nanostructure; a second gate structure (136) wrapping around the second nanostructures; a second source/drain epitaxial structure (128) formed beside the second nanostructures; and a second inner spacer (126; located proximate to nanostructure 116.2) between the second gate structure and the second source/drain epitaxial structure and having a second sidewall adjacent to the second gate structure, wherein the second sidewall of the second inner spacer (126; located proximate to nanostructure 116.2) is spaced apart from the first sidewall of the first inner spacer (126; located proximate to nanostructure 116.1) when viewed from above (Fig. 12A). Regarding Claim 2, Reboh discloses the semiconductor device structure as claimed in Claim 1, wherein sidewalls of the first gate structure are spaced apart from sidewalls of the second gate structure when viewed from above (Fig. 12A). Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 3-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 12,154,946 (“Li”). Although the claims at issue are not identical, they are not patentably distinct from each other because the differences in claim language amounts to rewording already protected limitations in the cited patent. Pending Claim 3 is unpatentable in view of patented Claim 1. The pending application recites sidewalls of the first and second inner spacers, adjacent to the respective gate structures, be spaced apart from each other in a vertical direction. This limitation is achieved by having gate structures with sidewalls that are not aligned in a vertical direction, which the cited patent already protects. A rewording of this protected limitation is not found to provide patentable distinction. Pending Claim 4 is unpatentable in view of patented Claim 18. Pending Claim 5 is unpatentable in view of patented Claim 18 since the inner spacers would have thicknesses similar to the gate structure. Pending Claim 6 is unpatentable in view of patented Claim 17. Pending Claim 7 is unpatentable in view of patented Claim 20. Pending Claim 8 is unpatentable or otherwise obvious over patented Claim 1 as it recites a method which would have resulted in the device of patented Claim 1. Pending Claim 9 is obvious in view of patented Claim 1 since the sacrificial layers (first and third semiconductor layers) are selectively removed, leaving channel layers (second and fourth semiconductor layers) intact. Pending Claim 10 is unpatentable in view of patented Claim 15. Pending Claim 11 is obvious in view of patented Claim 18. Pending Claim 12 is unpatentable in view of patented Claim 18. Pending Claim 13 is unpatentable in view of patented Claim 1. Pending Claim 14 is obvious in view of patented Claim 15. Pending Claim 15 is unpatentable or otherwise obvious over patented Claim 1 as it recites a method which would have resulted in the device of patented Claim 15. Pending Claim 16 is unpatentable in view of patented Claim 16 Pending Claims 17 and 18 are unpatentable or otherwise obvious over patented Claims 1 and 7 as they recite a method which would have resulted in the device of patented Claims 7 and 8. Pending Claim 19 is unpatentable in view of patented Claim 7. Pending Claim 20 is unpatentable in view of patented Claim 15. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID C SPALLA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 16, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772513
SEMICONDUCTOR DEVICE WITH IMPROVED SOURCE/DRAIN PROFILE AND METHODS OF FABRICATION THEREOF
3y 3m to grant Granted Oct 20, 2026
Patent 12765267
SEMICONDUCTOR DEVICE INCLUDING MAGNETIC TUNNEL JUNCTION STRUCTURE
2y 10m to grant Granted Oct 13, 2026
Patent 12764979
Semiconductor structure with a deep trench capacitor structures and forming method thereof
2y 7m to grant Granted Oct 13, 2026
Patent 12757734
PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME
5y 2m to grant Granted Oct 06, 2026
Patent 12757440
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
3y 7m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
89%
With Interview (+4.7%)
2y 3m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 857 resolved cases by this examiner. Grant probability derived from career allowance rate.

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