Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 10/16/24. Claims 2-21 are pending in this application.
Information Disclosure Statement
The information disclosures statements filed on 10/16/24, 09/25/25, 01/21/26, 05/08/26 and 08/19/26 have been received and are being considered.
Claim rejections under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2-17 and 20 are rejected under 35 U.S.C .§102 (a)(2) as being unpatentable over Xu (US 20220093370 A1).
Regarding claim 2, Xu discloses a semiconductor processing chamber emissivity liner (see fig 1, element 104), comprising: an annular body comprising a top surface, a bottom surface, an outer surface, and an inner surface (see annular 104, fig 1), wherein: the annular body defines a central opening (top opening); each of the inner surface and the outer surface extends between the top surface and the bottom surface (see inner surface 104); the inner surface of the annular body comprises an emissivity texture (see para [0041] disclosing texture); and the emissivity texture comprises a laser-textured pattern (see para [0038]) disclosing laser texture, the laser-textured pattern comprising etched and non-etch portions of the inner surface see figs 2b and 7 disclosing textured and non-textured areas.
Regarding claim 3, Xu discloses the semiconductor processing chamber emissivity liner of claim 2 wherein: the central opening is sized to receive a support plate of a substrate support (see fig 1, where support plate is located within opening esc 108).
Regarding claim 4, Xu discloses the semiconductor processing chamber emissivity liner of claim 2wherein: the emissivity texture comprises a plurality of microstructures (see figs 2a/b, 7, para [0046]).
Regarding claim 5, Xu discloses the semiconductor processing chamber emissivity liner of claim 2 wherein: the emissivity texture comprises a plurality of nanostructures(see figs 2a/b, 7) (para [0039]).
Regarding claim 6, Xu discloses the semiconductor processing chamber emissivity liner of claim 2 wherein: the emissivity texture is substantially uniform about an entire circumference of the annular body (see para [0052] disclosing substantial uniformity).
Regarding claim 7, Xu discloses the semiconductor processing chamber emissivity liner of claim 2 wherein: the emissivity texture extends about only a portion of a circumference of the annular body (see para [0037] disclosing partial texturing).
Regarding claim 8, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, wherein: the emissivity texture comprises a variable emissivity level about a circumference of the annular body (see figs 2a/b, 7 disclosing variable texture).
Regarding claim 9, Xu discloses the semiconductor processing chamber emissivity liner of claim 2 wherein: the emissivity texture comprises a plurality of dimples formed in the inner surface of the annular body(see figs 2a/b, 7 disclosing dimples).
Regarding claim 10, Xu discloses the semiconductor processing chamber emissivity liner of claim 9, wherein: the emissivity texture comprises a first emissivity region and a second emissivity region; and the first emissivity region comprises a greater dimple density than the second emissivity region(see figs 2a/b, 7 disclosing different dimple densities and regions).
Regarding claim 11, Xu discloses the semiconductor processing chamber emissivity liner of claim 9, wherein: the emissivity texture comprises a first emissivity region and a second emissivity region; and the first emissivity region comprises larger dimples than the second emissivity region(see figs 2a/b, 7 disclosing different dimple densities and regions, some are larger/smaller).
Regarding claim 12, Xu discloses the semiconductor processing chamber emissivity liner of claim 9, wherein: each of the plurality of dimples has a diameter of less than about 50 microns(see figs 2a/b, 7 disclosing different dimple densities and regions, see para [0045] disclosing micron range).
Regarding claim 13, Xu discloses the semiconductor processing chamber emissivity liner of claim 9, wherein: each of the plurality of dimples has a depth of less than about 50 microns(see figs 2a/b, 7 disclosing different dimple densities and regions, see paras [0045] and [0039] disclosing nanostructures).
Regarding claim 14, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, wherein: an emissivity level of the emissivity texture is between about 0.05 and 0.95 (see para [0029]).
Regarding claim 15, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, wherein: the emissivity texture covers only a portion of the inner surface (see para [0049] disclosing portion coverage).
Regarding claim 16, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, wherein: the emissivity texture comprises a plurality of arc-shaped regions, each arc- shaped region having a different emissivity level(see figs 2a/b, 7 disclosing different dimple densities and regions, see para [0045] disclosing micron range).
Regarding claim 17, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, wherein: the annular body defines a circumferential pumping cavity; and the annular body defines a plurality of exhaust ports that extend through a thickness of a sidewall and are fluidly coupled with the circumferential pumping cavity (see para [0022]).
Regarding claim 20, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, wherein: the annular body comprises a dielectric material (see para [0050] disclosing silicon)
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 19, 21 are rejected under 35 U.S.C. §103 as being unpatentable over Xu as applied to claim 2 and further in view of Curran (US 20140318974 A1).
Regarding claim 18, Xu discloses the semiconductor processing chamber emissivity liner of claim 2, but does not explicitly disclose wherein: the annular body comprises a conductive material. However, Curran is directed towards Plasma chamber liners and at least at paras [0005] and [0041] discloses a metal conductive liner, Al.
Xu and Curran are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Xu with Curran. Xu and Curran may be combined by forming the device of Xu with the material disclosed in Curran. One having ordinary skill in the art would be motivated to combine Xu with Curran in order to increase process uniformity, see paras [0005] and [0041].
Regarding claim 19, Xu and Curran disclose the semiconductor processing chamber emissivity liner of claim 18, wherein: the conductive material comprises aluminum(Curran at least at paras [0005] and [0041] discloses a metal conductive liner, Al.).
Regarding claim 21, Xu discloses the semiconductor processing chamber emissivity liner of claim 20, wherein: the dielectric material comprises aluminum nitride. However, Curran is directed towards Plasma chamber liners and at least at paras [0005] and [0041] discloses a metal liner, Al.
Xu and Curran are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Xu with Curran. Xu and Curran may be combined by forming the device of Xu with the material disclosed in Curran. One having ordinary skill in the art would be motivated to combine Xu with Curran in order to increase process uniformity, see paras [0005] and [0041].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
