CTNF 18/919,172 CTNF 76892 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA 2. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 3. Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In line 2 of claim 11, the phrase “3 σ average surface” (emphasis added) is indefinite because applicants fail to disclose the meaning of symbol “σ”. For purpose of examination, the examiner will interpret symbol “σ” stands for standard deviation. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA 6. Claim s 1-6, 8-10, 12-13, 15-19 are rejected under 35 U.S.C. 102( a)(1) and/or 102(a)(2 ) as being anticipated by Luan et al. (US 2022/0254645 A1), herein after refer as Luan (‘645) . As to claim 1 , Luan (‘645) discloses a semiconductor processing method comprising: providing a fluorine-containing precursor (i.e. NF 3 ) and a nitrogen-containing precursor (N 2 ) to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein alternating layers of silicon-and-germanium-containing material (108) and silicon-containing material (110) are disposed on the substrate (106) (See paragraph 0020-0023, 0039); forming plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor (paragraph 0034-0039, 0060); and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor, wherein the contacting selectively removes a portion of the silicon-and-germanium-containing material (108) (0029-0039). As to claim 2 , Luan (‘645) discloses wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF 3 ) (See paragraph 0038-0042). As to claim 3 , Luan (‘645) discloses wherein the nitrogen-containing precursor comprises diatomic nitrogen (N 2 ) (See paragraph 0038-0039). As to claim 4 , Luan (‘645) discloses wherein the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor are capacitively coupled plasma (CCP) effluents ( paragraph 0030; 0038-0039). As to claim 5 , Luan (‘645) discloses wherein the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor are formed at a plasma power of less than 400 W, including examples of 100 W (See paragraph 0040-0043; read on applicant’s range of “less than or about 1,000 W”). As to claim 6 , Luan (‘645) discloses the silicon-containing material comprises silicon (paragraph 0022). As to claim 8 , Luan (‘645) discloses wherein a temperature within the semiconductor processing chamber is maintained at a temperature between -40 °C to 20 ° (See paragraph 0043, read on applicant’s range of “less than or about 100 °C). As to claim 9 , Luan (‘645) discloses wherein a pressure within the semiconductor processing chamber is maintained at less than about 100 mTorr, including example of 15 mTorr to 25 mTorr (See paragraph 0043, read on applicant’s range of “less than or about 10 Torr” since 10 Torr = 10,000 mTorr). As to claim 10 , Luan (‘645) discloses wherein the silicon-and-germanium-containing material is removed relative to the silicon-containing material at a selectivity of greater than or equal to 50:1 (See paragraph 0053; read on applicant’s range “greater than or about 1.5:1). As to claim 12 , Luan (‘645) discloses a semiconductor processing method comprising: providing a fluorine-containing precursor and diatomic nitrogen (N 2 ) to a processing region of a semiconductor processing chamber, wherein a substrate (106)is housed within the processing region, wherein alternating layers of silicon-and-germanium-containing material (108) and silicon-containing material (110) are disposed on the substrate (paragraph 0022-0023; 0035-0041; forming capacitively coupled plasma (CCP) effluents of the fluorine-containing precursor and N 2 (paragraph 0030, 0035-0044; and contacting the substrate with the CCP effluents of the fluorine-containing precursor and N 2 , wherein the contacting selectively removes a portion of the silicon-and-germanium-containing material, and wherein a temperature within the semiconductor processing chamber is maintained at a temperature between -40 °C to 20 °C (paragraph 0035-0044, 0053; read on applicants temperature of “less than or about 100 °C). As to claim 13 , Luan (‘645) discloses wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF 3 ) (paragraph 0037-0039, 0042, 0044). As to claim 15 , Luan (‘645) discloses wherein the CCP effluents of the fluorine-containing precursor and N 2 are formed at a plasma power of less than about 400 W (See paragraph 0030, 0038-0039;0043-0044; read on applicant’s range of “less than or about 500 W”). As to claim 16 , Luan (‘645) discloses wherein a temperature within the semiconductor processing chamber is maintained at a temperature between -40 °C to 20 °C (paragraph 0043, read on applicant’s range of “less than or about 50 °C). As to claim 17 , Luan (‘645) discloses wherein a pressure within the semiconductor processing chamber is maintained at less than 100 mTorr, including example of 15 mTorr to 25 mTorr (paragraph 0043, read on applicant’s range of “less than or about 7 Torr” since 7 Torr = 7,000 mTorr). As to claim 18 , Luan (‘645) discloses a semiconductor processing method comprising: etching a portion of a silicon-and-germanium-containing material (108) from a substrate (106) disposed within a processing region of a semiconductor processing chamber, wherein the silicon-and-germanium-containing material (108) is one material of one or more alternating layers of material on the substrate, and wherein the silicon-and-germanium-containing material is characterized by a first average surface roughness (R a ) (paragraph 0022-0024, 00358-0040, 0053; Note: all material/layer has average surface roughness value); subsequent to etching the silicon-and-germanium-containing material, providing a fluorine-containing precursor and a nitrogen-containing precursor to the processing region of the semiconductor processing chamber (paragraph 0035-0042,); forming plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor (paragraph 0035-0042,; and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor, wherein the contacting removes an additional portion of the silicon-and-germanium-containing material (paragraph 0035-0042, 0050-0053). As to claim 19 , Luan (‘645) discloses performing a dry etch prior to etching a portion of the silicon-and-germanium containing material (Fig 2, step 206, paragraph 0015) . 07-15 AIA 7. Claim s 1-9, 12-19 are rejected under 35 U.S.C. 102( a)(1) and/or 102(a)(2 ) as being anticipated by Luan et al. (US 2022/0238309 A1), herein after refer as Luan (‘309) . As to claim 1 , Luan (‘309) discloses a semiconductor processing method comprising: providing a fluorine-containing precursor (i.e. NF 3 ) and a nitrogen-containing precursor (N 2 ) to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein alternating layers of silicon-and-germanium-containing material (108) and silicon-containing material (110) are disposed on the substrate (106) (See paragraph 0024-0029; 0039-0044); forming plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor; (paragraph 0039-0049) and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor, wherein the contacting selectively removes a portion of the silicon-and-germanium-containing material (108) (0039-0044, Fig 1D). As to claim 2 , Luan (‘309) discloses wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF 3 ) (See paragraph 0041-0049). As to claim 3 , Luan (‘309) discloses wherein the nitrogen-containing precursor comprises diatomic nitrogen (N 2 ) (See paragraph 0041-0047). As to claim 4 , Luan (‘309) discloses wherein the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor are capacitively coupled plasma (CCP) effluents ( paragraph 0033; 0041-0047). As to claim 5 , Luan (‘309) discloses wherein the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor are formed at a plasma power of 50 W to 500 Watt including examples of 200 W (See paragraph 0043; read on applicant’s range of “less than or about 1,000 W”). As to claim 6 , Luan (‘309) discloses the silicon-containing material comprises silicon (paragraph 0026). As to claim 7 , Luan (‘309) discloses to use NF3 at flow rate of 40 sccm, and N 2 at flow rate 250 sccm (paragraph 0044). Any person having ordinary skill in the art would be able to calculate that the flow rate ratio of nitrogen (N 2 ) precursor relative to fluorine precursor (NF 3 ) equal to 250:40 = 6.25:1 (read on applicant’s range of “greater than or about 2:1). As to claim 8 , Luan (‘309) discloses wherein a temperature within the semiconductor processing chamber is maintained at a temperature between -20 °C to 40 ° (See paragraph 0043, read on applicant’s range of “less than or about 100 °C). As to claim 9 , Luan (‘309) discloses wherein a pressure within the semiconductor processing chamber is maintained at a pressure of 100 mTorr to 500 mTorr (See paragraph 0043, read on applicant’s range of “less than or about 10 Torr” since 10 Torr = 10,000 mTorr). As to claim 12 , Luan (‘309) discloses a semiconductor processing method comprising: providing a fluorine-containing precursor and diatomic nitrogen (N 2 ) to a processing region of a semiconductor processing chamber, wherein a substrate (106)is housed within the processing region, wherein alternating layers of silicon-and-germanium-containing material (108) and silicon-containing material (110) are disposed on the substrate (paragraph 0024-0044); forming capacitively coupled plasma (CCP) effluents of the fluorine-containing precursor and N 2 (paragraph 0033, 0039-0049 and contacting the substrate with the CCP effluents of the fluorine-containing precursor and N 2 , wherein the contacting selectively removes a portion of the silicon-and-germanium-containing material, and wherein a temperature within the semiconductor processing chamber is maintained at a temperature between -20 °C to 40 °C (paragraph 0039-0043 read on applicants temperature of “less than or about 100 °C). As to claim 13 , Luan (‘309) discloses wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF 3 ) (paragraph 0040-0044). As to claim 14 , Luan (‘309) discloses to use N2 at 50 sccm to 300 sccm and NF3 at 20 sccm (paragraph 0043). Any person having ordinary skill in the art would be able to calculate a flow rate ratio of N 2 to NF 3 as shown below: N 2 = 50 sccm; NF 3 = 20 sccm; ratio of N 2 to NF 3 = 50:20 = 2.5:1 N 2 = 300 sccm; NF 3 = 20 sccm; ratio of N 2 to NF 3 = 300:20 = 15:1 Therefore, Luan (‘309) discloses the flow rate ratio of N 2 relative to NF 3 between 2.5:1 to 15:1 (Note: 15:1 read on applicant’s range of “greater than or about 10:1”). As to claim 15 , Luan (‘309) discloses wherein the CCP effluents of the fluorine-containing precursor and N 2 are formed at a plasma power of 50 W to 500 W (See paragraph 0033, 0043; read on applicant’s range of “less than or about 500 W”). As to claim 16 , Luan (‘309) discloses wherein a temperature within the semiconductor processing chamber is maintained at a temperature between -20 °C to 40 °C (paragraph 0043, read on applicant’s range of “less than or about 50 °C”). As to claim 17 , Luan (‘309) discloses wherein a pressure within the semiconductor processing chamber is maintained at pressure of 100 mTorr to 500 mTorr (paragraph 0043, read on applicant’s range of “less than or about 7 Torr” since 7 Torr = 7,000 mTorr). As to claim 18 , Luan (‘309) discloses a semiconductor processing method comprising: etching a portion of a silicon-and-germanium-containing material (108) from a substrate (106) disposed within a processing region of a semiconductor processing chamber, wherein the silicon-and-germanium-containing material (108) is one material of one or more alternating layers of material on the substrate, and wherein the silicon-and-germanium-containing material is characterized by a first average surface roughness (R a ) (paragraph 0026-0049; Note: all material/layer has average surface roughness value); subsequent to etching the silicon-and-germanium-containing material, providing a fluorine-containing precursor and a nitrogen-containing precursor to the processing region of the semiconductor processing chamber (paragraph 0039-0049,); forming plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor (paragraph 0039-0049; and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor, wherein the contacting removes an additional portion of the silicon-and-germanium-containing material (paragraph 0039-0049). As to claim 19 , Luan (‘309) discloses performing a dry etch prior to etching a portion of the silicon-and-germanium containing material (paragraph 0018, 0030) . Claim Rejections - 35 USC § 103 07-20-aia AIA 8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA 9. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-22-aia AIA 10. Claim s 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Luan (US 2022/0254645 A1) as applied to claim s 1, 18 above, and further in view of Hsu et al. (US 2024/0355906 A1) As to claim 11 , Luan (‘645) fails to disclose subsequent to removing the portion of the silicon-and-germanium-containing material, a 3σ average surface roughness (R a ) of the silicon-and-germanium-containing material is less than or about 5 nm. However, Luan (‘645) clearly discloses removing a portion of the silicon-and-germanium-containing material. Hsu teaches an method for etching layer on the substrate, wherein the layer comprises silicon-and-germanium (paragraph 0035, 0043, 0066-0067). Hsu further discloses subsequent to removing the portion of the silicon-and-germanium-containing material, a 3σ average surface roughness (R a ) of the silicon-and-germanium-containing material is between 0 nm and 5 nm (paragraph 0071). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Luan (‘645) in view of Hsu by having subsequent to removing the portion of the silicon-and-germanium-containing material, a 3σ average surface roughness (R a ) of the silicon-and-germanium-containing material is less than or about 5 nm because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)). As to claim 20 , Luan (‘645) fails to disclose subsequent to removing the portion of the silicon-and-germanium-containing material, the average surface roughness (R a ) of the silicon-and-germanium-containing material is improved by greater than or about 10% relative to the first average surface roughness (R a ). However, Luan (‘645) clearly discloses removing a portion of the silicon-and-germanium-containing material. Hsu teaches an method for etching layer on the substrate, wherein the layer comprises silicon-and-germanium (paragraph 0035, 0043, 0066-0067). Hsu further discloses subsequent to removing the portion of the silicon-and-germanium-containing material, the average surface roughness (R a ) of the silicon-and-germanium-containing material is improved by greater than or about 10% relative to the first average surface roughness (R a ) (paragraph 0071). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Luan (‘645) in view of Hsu by having subsequent to removing the portion of the silicon-and-germanium-containing material, the average surface roughness (R a ) of the silicon-and-germanium-containing material is improved by greater than or about 10% relative to the first average surface roughness (R a ) because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)) . 07-22-aia AIA 11. Claim s 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Luan (US 2022/0238309 A1) as applied to claim s 1, 18 above, and further in view of Hsu et al. (US 2024/0355906 A1) As to claim 11 , Luan (‘309) fails to disclose subsequent to removing the portion of the silicon-and-germanium-containing material, a 3σ average surface roughness (R a ) of the silicon-and-germanium-containing material is less than or about 5 nm. However, Luan (‘309) clearly discloses removing a portion of the silicon-and-germanium-containing material. Hsu teaches an method for etching layer on the substrate, wherein the layer comprises silicon-and-germanium (paragraph 0035, 0043, 0066-0067). Hsu further discloses subsequent to removing the portion of the silicon-and-germanium-containing material, a 3σ average surface roughness (R a ) of the silicon-and-germanium-containing material is between 0 nm and 5 nm (paragraph 0071). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Luan (‘309) in view of Hsu by having subsequent to removing the portion of the silicon-and-germanium-containing material, a 3σ average surface roughness (R a ) of the silicon-and-germanium-containing material is less than or about 5 nm because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)). As to claim 20 , Luan (‘309) fails to disclose subsequent to removing the portion of the silicon-and-germanium-containing material, the average surface roughness (R a ) of the silicon-and-germanium-containing material is improved by greater than or about 10% relative to the first average surface roughness (R a ). However, Luan (‘309) clearly discloses removing a portion of the silicon-and-germanium-containing material. Hsu teaches an method for etching layer on the substrate, wherein the layer comprises silicon-and-germanium (paragraph 0035, 0043, 0066-0067). Hsu further discloses subsequent to removing the portion of the silicon-and-germanium-containing material, the average surface roughness (R a ) of the silicon-and-germanium-containing material is improved by greater than or about 10% relative to the first average surface roughness (R a ) (paragraph 0071). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Luan (‘309) in view of Hsu by having subsequent to removing the portion of the silicon-and-germanium-containing material, the average surface roughness (R a ) of the silicon-and-germanium-containing material is improved by greater than or about 10% relative to the first average surface roughness (R a ) because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)). Conclusion 12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH X TRAN whose telephone number is (571)272-1469. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BINH X. TRAN Examiner Art Unit 1713 /BINH X TRAN/ Primary Examiner, Art Unit 1713 Application/Control Number: 18/919,172 Page 2 Art Unit: 1713
Prosecution Insights