DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,4-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0307118 A1 to Tu, “Tu”, in view of US 6,794,262 B2 to Ning et al., “Ning”.
Regarding claim 1, Tu discloses an integrated device (e.g. FIG. 5C), comprising:
a first bottom electrode layer (104, ¶ [0021]) comprising a first upper surface (recessed upper surface in outer 116);
a first top electrode layer (108, ¶ [0023]) disposed over the first bottom electrode layer and comprising a second upper surface (recessed upper surface in inner 116); and
a ferroelectric layer (106, ¶ [0022]) disposed between the first bottom electrode layer and the first top electrode layer and comprising a third upper surface (protruding surface) above the first upper surface and the second upper surface.
Tu fails to clearly teach one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric (ILD) layers over a substrate, with the first bottom electrode layer over one of the more lower interconnect layers.
Ning teaches (e.g. FIG. 10) one or more lower interconnect layers (348, column 7 line 66 to column 8 line 6) within one ore more stacked inter-layer dielectric (ILD) layers (346), with a first bottom electrode (326, column 7 line 39 to column 8 line 6) over one ore more lower interconnect layers.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Tu above an interconnect layer as exemplified by Ning in order to integrate the capacitor of Tu into a damascene wiring process with high capacitance density and reduced cost and production time (Ning column 1 line 47 to column 2 line 6, column 2 lines 36-49).
Regarding claim 4, Tu in view of Ning yields the integrated device of claim 1, and Tu further teaches (FIG. 5C) wherein the first upper surface (of 104) is substantially level with the second upper surface (of 108).
Regarding claim 5, Tu in view of Ning yields the integrated device of claim 1, and Tu further teaches (FIG. 5C) wherein the first upper surface (of 104) is the uppermost surface of the first bottom electrode layer (104).
Regarding claim 6, Tu in view of Ning yields the integrated device of claim 5, and Tu further discloses wherein the second upper surface (of 108) is the uppermost surface of the first top electrode layer (108), and wherein the first upper surface (of 104) is substantially level with the second upper surface (of 108).
Claims 7,11,12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0056107 A1 to Kuwajima, “Kuwajima”, in view of US 7,642,583 B2 to Hirano, “Hirano”.
Regarding claim 7, Kuwajima discloses an integrated device (FIG. 1), comprising:
a substrate (from FIG. 4 substrate “SB”, omitted in FIG. 1);
a first bottom electrode layer (“DE1”, ¶ [0059]) disposed over the substrate;
a first top electrode layer (“DE2”, ¶ [0059]) disposed over the first bottom electrode layer; and
a capacitor dielectric layer (B1b(B1) ¶ [0003],[0008],[0059],[0089]) disposed between and contacting a first surface (upper surface) of the first bottom electrode layer (“DE1”) and a second surface (bottom surface) of the first top electrode layer (“DE2”), wherein the capacitor dielectric layer (B1) comprises a protrusion (see Examiner-annotated figure below) extending past outer surfaces of the first top electrode layer (“DE2”) and the first bottom electrode layer (“DE1”) along a first direction (laterally) that is perpendicular to a second direction that is normal to the first surface, the protrusion confined between lines extending along the first surface and the second surface, wherein the protrusion has a thickness (T2) measured in the second direction, where the thickness (T2) is less than a distance (T3) between the first surface of the first bottom electrode layer (“DE1”) and the second surface of the first top electrode layer (“DE2”) measured in the second direction.
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Kuwajima fails to clearly teach wherein the capacitor dielectric layer (B1) is a ferroelectric layer.
Hirano teaches (e.g. Fig. 1(b) or 2(b)) wherein a capacitor dielectric (32a) is ferroelectric (Abstract, column 10 line 60 to column 11 line 2).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kuwajima with the capacitor dielectric formed of a ferroelectric material as taught by Hirano in order to form the ferroelectric memory cells of Hirano with the improved reliability and performance of the stepped (T3 to T2) thickness dielectric of Kuwajima (Kuwajima ¶ [0008],0012],[0013],[0161],[0169]).
Regarding claim 11, Kuwajima in view of Hirano yields the integrated device of claim 7, and Kuwajima further teaches wherein the capacitor dielectric layer (B1, ferroelectric when applied to Hirano) has a bottommost surface (horizontal in FIG. 1), and wherein the second direction (vertical in FIG. 1) is normal to the bottommost surface.
Regarding claim 12, Kuwajima in view of Hirano yields the integrated device of claim 7, and Kuwajima further teaches wherein the first bottom electrode layer (“DE1”) has a first width (see Examiner-annotated figure below) and the ferroelectric layer (B1) has a second width that is less than the first width.
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Allowable Subject Matter
Claims 13-20 are allowed.
Claims 2-3,8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Although prior art e.g. Tu teaches a ferroelectric layer having an exposed upward facing surface higher than the electrode layers as discussed above, prior art fails to reasonably teach or suggest wherein the ferroelectric layer has a first region extending from the third upper surface to a first distance below the third upper surface with a first surface roughness; wherein the ferroelectric layer has a second region extending below the first region with a second surface roughness, wherein the first surface roughness is greater than the second surface roughness as claimed in claim 2 together with all of the limitations of claim 1. Claim 3 is objected to as being allowable insofar as it depends upon and includes all of the limitations of claims 2 and 1.
Furthermore, although prior art e.g. Kuwajima teaches a capacitor with protrusions as discussed above and prior art e.g. Hirano teaches a ferroelectric capacitor dielectric, prior art fails to reasonably teach or suggest wherein the protrusion has a first surface with a first surface roughness, and a second surface with a second surface roughness that is less than the first surface roughness as claimed in claim 8 together with all of the limitations of claim 7. Similarly, prior art fails to reasonably teach or suggest wherein the protrusion has a first surface with a first surface roughness, and the first bottom electrode layer has a second surface with a second surface roughness that is less than the first surface roughness as claimed in claim 9 together with all of the limitations of claim 7.
Additionally, although prior art e.g. Tu teaches a ferroelectric capacitor dielectric having protrusions in a direction normal to a the ferroelectric bottom surface, prior art fails to reasonably teach or suggest , wherein the ferroelectric layer has a bottommost surface, and wherein the first direction is normal to the bottommost surface as claimed in 10 together with all of the limitations of claim 7.
Lastly, although prior art e.g. Tu teaches a ferroelectric having protrusions in the vertical direction and Kuwajima teaches a ferroelectric layer having protrusions in the lateral direction as discussed above, prior art fails to reasonably teach or suggest in sufficient detail wherein the first distance is measured in a first direction normal to the first surface, wherein the ferroelectric layer further comprises a fourth surface a second distance from the first surface measured in the first direction, and a fifth surface a third distance from the first surface measured in the first direction, wherein the second distance is greater than the first distance, and the third distance is greater than the second distance, wherein the ferroelectric layer comprises a protrusion extending past outermost surfaces of the bottom electrode and the top electrode in a second direction perpendicular to the first direction, and wherein the third surface and the fourth surface surround the protrusion together with all of the other limitations of claim 13 as claimed. Claims 14-20 are allowable insofar as they depend upon and include all of the limitations of allowable claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 6,686,265 B2 to Beitel et al. teaches (Fig. 1) wherein a capacitor has a ferroelectric dielectric (13) with protrusions extending beyond the lower (11) and upper (12) electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
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