DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 10/21/2024. Applicant’s preliminary amendment filed on 01/16/2025 is being acknowledged and entered.
Claims 1-20 are pending. Claims 1, 9, and 19 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. No priority date is in the record, see ADS.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 01/20/2026. This IDS has been considered.
Specification Objections
6. Content of the disclosure “Background” section does not discuss any meaningful problem to be solved or background information and is objected to. 37 C.F.R. 1.71(b) requires, “The specification must set forth the precise invention for which a patent is solicited, in such manner as to distinguish it from other inventions and from what is old.” Applicant is reminded that helpful guidance, as to preparing an application disclosure, is provided in the MPEP under section 608. Notably, MPEP 608.01(c) provides exemplary use of the heading “Background of the Invention”.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8. Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 19, it recites: “…providing, upon identifying a memory circuit configured in a first operation mode, an operation voltage equal to the second supply voltage with a first logic state…”; and later clauses in the claim recites “…wherein, in the first operation mode, the first supply voltage and the second supply voltage are each provided with the second logic state…”: claim recites contradicting limitation, vague and ambiguous since it is not clear how second supply voltage can be supplied with both first logic state and second logic state in the first operation mode.
Claim 19, it recites: “…providing, upon identifying the memory circuit configured in a third operation mode, the operation voltage equal to the second supply voltage with the first logic state…”; and later clauses in the claim recites “…wherein, in the third operation mode, the first supply voltage and the second supply voltage are provided with the first logic state and the second logic state, respectively….”: claim recites contradicting limitation, vague and ambiguous since it is not clear how second supply voltage can be supplied with both first logic state and second logic state in the third operation mode. Claim language is vague and ambiguous and the specification does not provide a standard for ascertaining the language, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claim language must distinctly and particularly point out the invention. When a claim contains two or more contradictory limitations, it renders the claim's boundaries unascertainable, resulting in an indefiniteness rejection. (MPEP § 2173.02).
For art rejection, it was interpreted that during operation modes, both logic states of the power supply are being utilized.
All dependent claim inclusive of claims 19-20 are rejected under this category.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
11. Claims 1-3, 8-10, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2024/0146305 A1).
Regarding independent claim 1, Yu teaches a circuit (para [0016]: memory circuit), comprising:
a memory array comprising a plurality of memory cells (para [0016]: OTP memory array); and
a voltage provision circuit (Fig. 5: 500 “voltage provision circuit” associated with I/O circuit) configured to provide an operation voltage (Fig. 5: VDDQ output voltage) for one or more of the plurality of memory cells,
the operation voltage (Fig. 5: VDDQ) being shifted from a first voltage domain to a second voltage domain (see Fig. 3: L1 level shifter is used in generating output voltage VDDQ; and level shifter is between HVDD/ LVDD domain and VQPS domain);
wherein the voltage provision circuit comprises a voltage detector (Fig. 5: VD1 “VDD detector”), and
wherein the voltage detector (Fig. 5: VD1 “VDD detector”) is configured to receive a first supply voltage (para [0045]: VDD) in the first voltage domain, powered by a second supply voltage (para [0045]: VQPS) in the second voltage domain, and
provide a first control signal (Fig. 5: Vx),
the first control signal (para [0045], Fig. 5: Vx is based on based on VDD, VQPS comparison) being configured to determine (controls to determine or set voltage level) whether the operation voltage (Fig. 5: VDDQ) is equal to the second supply voltage at a first logic state (Fig. 5: VQPS high level) or the second supply voltage at a second logic state (Fig. 5: VQPS low level. See Fig. 5 in context of para [0045]: e.g., “…voltage detector VD1 can forcibly pull the output signal VDDQ to ground…”).
Regarding claim 2, Yu teaches the circuit of claim 1, wherein the voltage provision circuit further comprises:
a NOR gate (Fig. 5: NOR gate coupled to inputs Vx, input inverted PV and with 118 output) configured to receive the first control signal (Fig. 5: Vx) and provide a second control signal (Fig. 5: 118);
a first inverter (Fig. 5: inverter with 118 input) configured to receive the second control signal (Fig. 5: 118) and provide a third control signal (Fig. 5: 119); and
a second inverter (Fig. 5: inverter with 120 input) configured to receive the third control signal (Fig. 5: 119) and provide the operation voltage (para [0045]: VDDQ output is controlled);
wherein each of the NOR gate, the first inverter, and the second inverter is powered by the second supply voltage (Fig. 5: VQPS).
Regarding claim 3, Yu teaches the circuit of claim 1, wherein the voltage detector comprises a third inverter (Fig. 5: inverter with PV input within the circuitry segment of detector and operably coupled to the detector), powered by the second supply voltage (Fig. 5: VQPS), that is configured to receive the first supply voltage (Fig. 5: via PS, PD receives VDD) and provide the first control signal (since VD1, P2 are operably coupled, Vx and PD are taken to be first control signal related).
Regarding claim 8, Yu teaches the circuit of claim 1, wherein the plurality of memory cells each include a one-time-programmable (OTP) memory cell (para [0016]: OTP).
Regarding independent claim 9, Yu teaches a circuit (Fig. 5: 500 “voltage provision circuit” associated with I/O circuit), comprising:
a voltage detector (Fig. 5: VD1 “VDD detector”), powered by a first supply voltage (para [0045]: VQPS) in a first voltage domain (See para [0020]), that is configured to receive a second supply voltage (para [0045]: VDD) in a second voltage domain and provide a first control signal (Fig. 5: Vx, para [0045]),
wherein the first supply voltage at a logic high state is higher than the second supply voltage at the logic high state (See para [0020]: VQPS 1.8V, VDD 0.75V in high state);
a logic gate (Fig. 5: NOR connected to input PV and input Vx) configured to provide a second control signal (Fig. 5: pstb1) based on the first control signal (Fig. 5: Vx),
the first and second control signals being in the first voltage domain (para [0045]: VQPS domain); and
a first n-type transistor (Fig. 5: M25) having a gate terminal configured to receive the second control signal (Fig. 5: pstb1) through a first inverter (Fig. 5: inverter with 120 input),
a drain terminal (Fig. 5: drain of M25) coupled to an output node (Fig. 5: N11) for providing a memory circuit with an operation voltage (Fig. 5: VDDQ), and a source terminal (Fig. 5: source of M25) coupled to a ground voltage (Fig. 5: VSS);
wherein the second control signal (Fig. 5: pstb1) is outputted by the logic gate at the logic high state even if the first supply voltage is provided with the logic high state (Fig. 5: VQPS is high and VDD not ready results in Vx high 1) and the second supply voltage (Fig. 5: VDD is low result in PV being low 0) is provided with a logic low state (para [0045]: pstb1 high and N11 is pulled to ground. See also para [0028]-para [0029]).
Regarding claim 10, Yu teaches the circuit of claim 9, wherein the logic gate includes a NOR logic gate (para [0045]. Fig. 5: NOR gate coupled to inputs Vx, input inverted PV and with 118 output).
Regarding claim 17, Yu teaches the circuit of claim 9, wherein the voltage detector comprises an inverter, powered by the first supply voltage, that has an input configured to receive the second supply voltage and an output configured to provide the first control signal. (See claim 3 rejection analysis)
12. Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by YANG et al. (US 2022/0199124 A1)
Regarding independent claim 19, YANG teaches a method for providing an operation voltage to a memory circuit (Fig. 1: 100), comprising:
receiving a first supply voltage (Fig. 2: VDDM input) transitioning in a first voltage domain (Fig. 2: see level shifter and transition) and a second supply voltage (Fig. 2: VDD input) transitioning in a second voltage domain (Fig. 2: see level shifter and transition),
the first voltage domain being different from the second voltage domain (para [0028]);
providing, upon identifying a memory circuit configured in a first operation mode (Fig. 3: normal mode. See Row1), an operation voltage (Fig. 1-Fig. 3: VDDAI) equal to the second supply voltage with a first logic state (Fig. 1-Fig. 3: VDDAI high/ on);
providing, upon identifying the memory circuit configured in a second operation mode (Fig. 3: sleep mode. See Row2), the operation voltage equal to the second supply voltage (Fig. 1-Fig. 3: VDDAI) with a second logic state (Fig. 1-Fig. 3: VDDAI low/ off); and
providing, upon identifying the memory circuit configured in a third operation mode (Fig. 3: sleep mode in row4), the operation voltage equal to the second supply voltage (Fig. 1-Fig. 3: VDDAI) with the first logic state (Fig. 1-Fig. 3: high/ on);
wherein, in the first operation mode (Fig. 3: normal mode), the first supply voltage (Fig. 1-Fig. 3: VDDH) and the second supply voltage (Fig. 1-Fig. 3: VDDAI) are each provided with the second logic state (Fig. 3: both ON and OFF states are utilized in the normal mode operation process on both first power supply and second power supply),
wherein, in the second operation mode (Fig. 3: sleep mode), the first supply voltage (Fig. 1-Fig. 3: VDDH) and the second supply voltage (Fig. 1-Fig. 3: VDDAI) are each provided with the second logic state (Fig. 3: both ON and OFF states are utilized in the sleep mode operation process on both first power supply and second power supply), and
wherein, in the third operation mode (Fig. 3: sleep mode in row4), the first supply voltage (Fig. 1-Fig. 3: VDDH) and the second supply voltage (Fig. 1-Fig. 3: VDDAI) are provided with the first logic state and the second logic state (Fig. 3: both ON and OFF states are utilized in the sleep mode operation process on both first power supply and second power supply), respectively.
Allowable Subject Matter
Claims 4-7, 11-16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Chang (US20230043443A1): Fig. 1-Fig. 6A applicable for all claims
Verma et al. (US 2021/0005248 A1) is applicable for all claims
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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