DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Taiwan I790945).
Regarding claim 1, in Figure 1, Lee discloses a wiring substrate, comprising: a multilayer board structure (comprising 1a and 19) divided into an upper portion and a lower portion by a core layer (10) interposed therein, wherein the upper portion is used to connect to a die device (17), and the lower portion is used to connect to a circuit board (1b); a main ground area (16) located within the lower portion of the multilayer board structure; a wiring module (19) located on the multilayer board structure, and comprising a differential pair circuit and a plurality of ground via portions, the ground via portions that are electrically connected to the main ground area (Figure 1), respectively, and the differential pair circuit having two signal via portions arranged among the ground via portions; and a plurality of first dummy metal pads (pads not connected to balls 192) embedded in the lower portion, electrically isolated from the wiring module, spaced arranged between the differential pair circuit and the ground via portions, and between the signal via portions (Figure 1).
Regarding claim 2, Lee discloses wherein the first dummy metal pads are spaced arranged within the lower portion in a plane direction and a stacking direction, respectively, wherein the plane direction is orthogonal to the stacking direction (Figure 1).
Regarding claim 3, Lee discloses wherein some of the first dummy metal pads collectively surrounds one of the signal via portions (Figure 1).
Regarding claim 4, Lee discloses wherein a minimum straight spacing distance between one of the signal via portions and one of the first dummy metal pads is between 30 and 125 microns (Figure 1).
Regarding claim 5, Lee discloses a plurality of second dummy metal pads that are electrically isolated from the wiring module, wherein one side of the lower portion opposite to the upper portion is provided with a solder mask layer connected to the circuit board through a BGA layer, and the second dummy metal pads are embedded in the solder mask layer, and spaced arranged between the differential pair circuit and the ground via portions, and between the signal via portions (Figure 1).
Regarding claim 6, Lee discloses wherein a minimum straight spacing distance between one of the signal via portions and one of the second dummy metal pads is between 30 and 125 microns (Figure 1).
Regarding claim 7, Lee discloses wherein one of the first dummy metal pads and one of the second dummy metal pads are overlapped with each other in a stacking direction (Figure 1).
Regarding claim 8, Lee discloses wherein a width of one of the second dummy metal pads is smaller than a width of one of the first dummy metal pads (Figure 1).
Regarding claim 9, Lee discloses wherein a diameter of one section of one of the signal via portions in the core layer is greater than a diameter of another section of the one of the signal via portions in the lower portion (Figure 1).
Regarding claim 10, in Figure 1, Lee discloses a wiring substrate, comprising: a multilayer board structure comprising a core layer (10), a first solder mask layer (13), a second solder mask layer (15), at least one first dielectric layer (171) and at least one second dielectric layer (191), the core layer that is stacked between the at least one first dielectric layer and the at least one second dielectric layer (Figure 1), a thickness of the core layer that is greater than a thickness of the at least one second dielectric layer (Figure 1), the at least one first dielectric layer that is stacked between the first solder mask layer and the core layer (Figure 1), the first solder mask layer that is used to install a solder bump layer (14) thereon, the at least one second dielectric layer that is stacked between the second solder mask layer and the core layer (Figure 1), the second solder mask layer that is used to arrange a BGA layer (192) thereon, the at least one second dielectric layer comprising a first layer body and a plurality of first dummy metal pads (pads not connected to bumps 192) embedded within the first layer body and spaced arranged within the first layer body in a plane direction; a main ground area (16) located within the multilayer board structure; and a wiring module (19) comprising a differential pair circuit and a plurality of ground via portions, each of the ground via portions penetrating through the multilayer board structure, and electrically connected to the solder bump layer, the BGA layer and the main ground area, respectively, the differential pair circuit comprising two signal via portions, each of the signal via portions penetrating through the multilayer board structure, arranged among the ground via portions, and electrically connected to the solder bump layer and the BGA layer, wherein the first dummy metal pads are electrically isolated from the wiring module, and separated from the differential pair circuit and the ground via portions, respectively (Figure 1).
Regarding claim 11, Lee discloses wherein a first group of the first dummy metal pads is spaced arranged between the signal via portions, and a second group of the first dummy metal pads is spaced arranged between one of the signal via portions and one of the ground via portions (Figure 1).
Regarding claim 12, Lee discloses wherein the first group and the second group of the first dummy metal pads collectively surround one of the signal via portions (Figure 1).
Regarding claim 13, Lee discloses wherein one of the ground via portions is arranged between the second group of the first dummy metal pads and a third group of the first dummy metal pads (Figure 1).
Regarding claim 14, Lee discloses wherein a minimum straight spacing distance between one of the signal via portions and one of the first dummy metal pads is between 30 and 125 microns (Figure 1).
Regarding claim 15, Lee discloses wherein the at least one second dielectric layer comprises a plurality of second dielectric layers stacked sequentially in a stacking direction, and directly sandwiched between the core layer and the second solder mask layer, and the stacking direction is orthogonal to the plane direction, wherein the first dummy metal pads arranged within the second dielectric layers are overlapped with each other in the stacking direction (Figure 1).
Regarding claim 16, Lee discloses wherein the second solder mask layer comprises a second layer body and a plurality of second dummy metal pads embedded within the second layer body and spaced arranged in the plane direction, wherein the second dummy metal pads are electrically isolated from the wiring module, and separated from the differential pair circuit and the ground via portions, respectively (Figure 1).
Regarding claim 17, Lee discloses wherein a first group of the second dummy metal pads is spaced arranged between the signal via portions, and a second group of the second dummy metal pads is spaced arranged between one of the signal via portions and one of the ground via portions, wherein the main ground area is located on the second solder mask layer to surround the differential pair circuit and the second dummy metal pads (Figure 1).
Regarding claim 18, Lee discloses wherein a minimum straight spacing distance between one of the signal via portions and one of the second dummy metal pads is between 30 and 125 microns (Figure 1).
Regarding claim 19, in Figure 1, Lee discloses a wiring substrate, comprising: a multilayer board structure (comprising 1a and 19) divided into an upper portion and a lower portion by a core layer(10) interposed therein, the upper portion is used to connect to a die device (17), and the lower portion comprising a solder mask layer (15), a BGA layer (192) and at least one dielectric layer (191), the at least one dielectric layer that is stacked between the solder mask layer and the core layer, and the solder mask layer is located between the BGA layer and the at least one dielectric layer, and the BGA layer is used to connect to a circuit board (1b); a main ground area (16) located within the lower portion of the multilayer board structure; a wiring module (19) comprising a differential pair circuit and a plurality of ground via portions, each of the ground via portions penetrating through the multilayer board structure and electrically connected to the main ground area, the differential pair circuit comprising two signal via portions, each of the signal via portions penetrating through the multilayer board structure, arranged among the ground via portions; and a plurality of dummy metal pads embedded in one of the solder mask layer and the at least one dielectric layer, and arranged sequentially in a plane direction, wherein the dummy metal pads are spaced arranged between the differential pair circuit and the ground via portions, and between the signal via portions, and electrically isolated from the wiring module (Figure 1).
Regarding claim 20, Lee discloses wherein one group of the dummy metal pads is spaced arranged between the signal via portions, and another group of the dummy metal pads is spaced arranged between one of the signal via portions and one of the ground via portions, and the one group and the another group of the dummy metal pads collectively surround one of the signal via portions (Figure 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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