DETAILED ACTION
This office action is in response to the reply filed on 03/06/2026.
Claims 1-21 are pending in the application, with claims 8-19 having been withdrawn. Claims 1-7 and 20-21 have therefore been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the copy”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-7, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Citron (U.S. Patent 8,635,431) in view of Jayasena (U.S. Publication 2015/0155876).
Regarding claim 1, Citron discloses a memory apparatus, comprising: a set of one or more memory chips, containing at least two memory chips [Fig. 5; the system includes a memory hierarchy]; and a control logic, operable to direct operation of the set of one or more stacked memory chips and to communicate with at least one processing unit [col. 5, lines 1-12; a processor decodes a vector gather instruction and directs it to a vector gather buffer logic], copy requested data using a gather operation, requested by the at least one processing unit, from the set of one or more stacked memory chips to a gather accelerated address space [col. 5, lines 14-42; data is copied from the memory hierarchy to the vector gather buffer logic], the requested data is communicated to the at least one processing unit using the gather accelerated address space and the copy is requested by the at least one processing unit [col. 5, lines 14-42; data is read from the vector gather buffer logic and written to a vector register in the processor in response to a request], where the gather operation aligns the requested data to a byte chunk size specified by the at least one processing unit [col. 7, lines 35-53; the data is aligned based on the size of the vector register identified] and copies at least two non-contiguous byte segments corresponding to the requested data [col. 5, lines 14-42; Figures 5, 6; data is loaded from non-contiguous byte segments in the memory hierarchy]. Citron does not explicitly disclose that the memory chips are stacked. However, the use of stacked memory systems (also known as high-bandwidth memories) in systems such as Citron was well-known at the time of the effective filing date of the application. For example, Jayasena discloses [abstract] a die-stacked memory device for the purpose [paragraph 0037] of performing high-efficiency gather/scatter operations such as that disclosed in Citron. The benefits of memory stacking include higher performance which is critical for memory-intensive applications such as the gather operations disclosed by Citron, and the use of a stacked memory in Citron would therefore have been obvious to a person having skill in the art.
Regarding claim 2, Citron in view of Jayasena discloses the memory apparatus as recited in Claim 1, wherein the set of one or more stacked memory chips are dynamic random-access memory (DRAM) chips [Jayasena, paragraphs 0024-0025].
Regarding claim 3, Citron in view of Jayasena discloses the memory apparatus as recited in claim 1, wherein the processing unit is a graphics processing unit (GPU), a central processing unit (CPU), or a single instruction, multiple data processing unit (SIMD) [Citron, col. 1, lines 12-15; Jayasena, paragraph 0023].
Regarding claims 4 and 20, Citron in view of Jayasena discloses the memory apparatus as recited in Claim 1, wherein the gather accelerated address space is a virtual address space [Citron, col. 5, lines 28-52; col. 6, lines 19-48; the VGB uses effective addresses and there is a mapping between the addresses used in the VGB and the physical address of the data], wherein at least some unneeded memory sectors are not copied into the gather accelerated address space [col. 5, lines 14-42; col. 7, lines 35-53; the operation does not copy every sector in the memory as part of the operation; the operation only copies specified portions of memory].
Regarding claims 6 and 21, Citron in view of Jayasena discloses the memory apparatus as recited in Claim 1, wherein one or more gather instructions of the gather operation are executed asynchronously to other instructions performed by the control logic [Citron, col. 5, lines 7-8; a vector gather instruction is executed; col. 8, lines 3-9; other operations may asynchronously modify the data such that a coherency protocol is required].
Regarding claim 7, Citron in view of Jayasena discloses the memory apparatus as recited in Claim 1, wherein the byte chunk size can be one or more of 1Byte (B), 2B, 4B, 8B, or 16B [Citron, col. 2, lines 54-56; the vector size is 16 bytes].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Citron in view of Jayasena and Leidel (U.S. Patent 10,838,865).
Regarding claim 5, Citron in view of Jayasena does not explicitly disclose control logic in a base layer of the stacked memory. However, Leidel discloses [col. 2, lines 42-54] a stacked memory system having control logic in a base layer for the purpose of controlling memory operations such as those disclosed in Citron in view of Jayasena. Placing the control logic adjacent to the stacked memory allows for faster communication and such operation would therefore have been obvious in the system of Citron in view of Jayasena.
Response to Arguments
Applicant's arguments filed 03/06/2026 have been fully considered but they are not persuasive.
Applicant argues that Citron does not utilize a byte chunk size specified by a processing unit. However, this limitation is much broader than applicant is apparently arguing for and is inherent in the operation of the rest of the claimed invention. If a processing unit utilizes a certain byte chunk size, that byte chunk size is inherently “specified by” the processing unit. In other words, the use of that size is itself a specification of the size. Applicant’s argument is therefore not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COREY S FAHERTY/Primary Examiner, Art Unit 2183
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