Prosecution Insights
Last updated: April 19, 2026
Application No. 18/929,742

METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, RECORDING MEDIUM, AND SUBSTRATE PROCESSING APPARATUS

Non-Final OA §102§103
Filed
Oct 29, 2024
Examiner
HERNANDEZ-KENNEY, JOSE
Art Unit
1717
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Kokusai Electric Corporation
OA Round
1 (Non-Final)
54%
Grant Probability
Moderate
1-2
OA Rounds
3y 4m
To Grant
77%
With Interview

Examiner Intelligence

Grants 54% of resolved cases
54%
Career Allow Rate
315 granted / 588 resolved
-11.4% vs TC avg
Strong +23% interview lift
Without
With
+23.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
44 currently pending
Career history
632
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
44.7%
+4.7% vs TC avg
§102
17.6%
-22.4% vs TC avg
§112
29.7%
-10.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 588 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1 – 17 in the reply filed on December 1, 2025 is acknowledged. Claims 18 – 20 are withdrawn from consideration. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 5, 9 – 11, 13, 16 – 17 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Wang et al. US 20230068625 A1 (hereinafter “Wang”). Regarding claims 1, 9, 16, 17: Wang is directed to semiconductor structures that include a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer and a conductive via (Abstract). Wang discloses embodiments of their method comprising: providing a substrate wafer 110 having conductive features 130 [surface of a first material], dielectric layer 120 [surface of a second material], and conductive feature 132 [surface of a third material] (Fig. 1; [0010], [0014] – [0016]); selectively forming an inhibitor film 140 [first sacrificial and second sacrificial films] over conductive features 130 and 132 ([0016]; Fig. 2); depositing an etch stop layer 150 [isolation film] over the dielectric layer 120 wherein the inhibitor film 140 sides act as sidewalls to the etch stop layer 150 [recesses], including any steps for planarization for cleaning excess deposited materials such as etch stop layer ([0015], [0019]; Fig. 3); selectively etching the inhibitor film 140 to reveal the top surfaces of conductive features 130 and 132 within recesses formed from the etch stop layer 150 ([0023], Fig. 4). Regarding claim 2: Wang discloses that the conductive features 130 and 132 [first material and third material] may be a metal such as cobalt [non-oxides] ([0015]). The dielectric material 120 may be an oxide such as silicon oxide ([0014]). Regarding claim 5: Wang discloses that the etch stop layer 150 may be a metal oxide ([0021]). Regarding claim 10 – 11, 13: Wang further discloses that their method may further comprise: depositing capping layers 160 onto the conductive features 130 and 132, which are in contact with the first etch stop layer 150 and the conductive features 103 and 132 ([0024] – [0027]; Fig. 5). The capping layers may be a high-K dielectric such as titanium dioxide that initially covers the etch stop layer before a planarization process removes excess material. Claim(s) 1 – 7, 10, 12 – 13, 15, 17 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sandhu et al. US 20180315771 A1 (hereinafter “Sandhu”). Regarding claims 1, 7, 17: Sandhu is directed to arrays of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels, wordline levels and methods of making such stacks (Abstract). As depicted in Fig. 17 and 18, Sandhu discloses that embodiments of their method comprises: providing a substrate stack 15 having an end-structure with a third material 69 with surfaces 59 [first and third material in the context of the present claim], and a surface 38 of a second material 26 adjacent to one each of the third material sequentially, wherein the surface termination at the end of the second material acts as a first adsorption inhibition layer ([0057] – [0058]); selectively bonding an organic monolayer from precursors onto the surfaces of the third material 69 [first and second sacrificial films] ([0058]); depositing an insulative material 80 [isolation films] onto the surfaces 38, wherein the organic monolayer acts as a thin sidewall ([0059]; Fig. 18); and removing the organic monolayer to fully reveal surfaces 59 embedded [recessed] between protrusions of insulative material 80 ([0060]; Fig. 18). Regarding claim 2 – 4: Sandhu discloses that the second material 26 with surface 38 may be silicon dioxide ([0038]), while the third material 69 [corresponding to first and third materials] with surface 59 may be silicon nitride or metal nitrides of e.g. molybdenum, or tungsten ([0041]). Regarding claims 5, 6: Sandhu discloses that the insulative material 80 may be e.g silicon oxide ([0059]). Regarding claims 10, 12 – 15: Sandhu further discloses that their method may further comprise: depositing a second absorption inhibition layer onto the insulative layer to allow the deposition of a charge-storage material 44 within the recesses formed between the peaks of the insulative material 80, wherein the charge-storage material may be e.g. silicon nitride [first and second dielectric films ([0032], [0060] – [0062]). Claim Rejections - 35 USC § 103 This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sandhu as applied to claims 1 – 7, 10, 12 – 13, 15, 17 above. Regarding claim 8: Sandhu does not expressly teach that within the step of selectively forming a first sacrificial form on the surface of the recited first material, that protrudes to the surface of the second material as recited. However, real world depositions are not ideal and, while selective, there is an expectation of some spill-over in boundaries of deposited films, including the first sacrificial film. It would then be readily apparent within the standard practice of one of ordinary skill in the art that the limitations in claim 8 would have been met by practice of the disclosed method under routine conditions with an expectation that such spill-over can occur. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE I HERNANDEZ-KENNEY whose telephone number is (571)270-5979. The examiner can normally be reached M-F 6:30-3:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dah-Wei Yuan can be reached on (571) 272-1295. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSE I HERNANDEZ-KENNEY/ Primary Examiner Art Unit 1717
Read full office action

Prosecution Timeline

Oct 29, 2024
Application Filed
Mar 17, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
54%
Grant Probability
77%
With Interview (+23.2%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 588 resolved cases by this examiner. Grant probability derived from career allow rate.

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