Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7 - 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jojima (US 20190245443).
Regarding claim 1, Jojima discloses a device package comprising:
a plurality of power devices (the power converter 10, Fig. 8) arranged to provide a power circuit having a first input (input circuit connected to terminal 54, paragraph 65), a second input (input circuit 60 connected to terminal 55; paragraph 65), and at least one output (the output circuit 52 connected to terminals 52a – 52c; paragraph 63);
at least one first input power terminal (54) providing the first input for the power circuit;
at least one second input power terminal (55) providing the second input for the power circuit;
at least one output power terminal (52a – 52c) providing the at least one output for the power circuit; and
a housing (the case 70) for the plurality of power devices and portions of the at least one first input power terminal (54), the at least one second input power terminal (55), and the at least one output power terminal (52a – 52c), the housing having a top side (left surface of the housing; Fig. 9), a bottom side (right surface of the housing) opposite the top side, and a first side (the side between the left surface and the bottom surface) extending from the top side to the bottom side, the top side having a greater surface area relative to the first side;
wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend out of the first side of the housing (terminals 54, 55, 52 – 52c are on the same side; Fig. 8).
Regarding claim 3, Jojima discloses the claimed invention as set forth in claim 1. Jojima further suggests the at least one output power terminal comprises a first output power terminal (52a) providing a first output of the power circuit, a second output power terminal (52b) providing a second output of the power circuit, and a third output power terminal (52c) providing a third output of the power circuit.
Regarding claim 7, Jojima discloses the claimed invention as set forth in claim 1. Jojima suggests the at least one first input power terminal or the at least one second input power terminal is directly mechanically coupled to a substrate (plates 71, Fig. 9).
Regarding claim 8, Jojima discloses the claimed invention as set forth in claim 1. Jojima suggests the at least one first input power terminal and the at least one second input power terminal are directly mechanically coupled to a substrate (plates 71, Fig. 9).
Regarding claim 9, Jojima discloses the claimed invention as set forth in claim 8. Jojima further suggests the at least one output power terminal is not directly mechanically coupled to a substrate (41a, Fig. 6), and bond wires (the wire bond 47 connect a substrate to a terminal) couple the at least one output power terminal to the power circuit.
Regarding claim 10, Jojima discloses the claimed invention as set forth in claim 9. Jojima further suggests at least one of a plurality of signal terminals is directly mechanically coupled to a substrate (terminal 6n connected to the substrate 45 and 413; Fig. 4), and at least one other of the plurality of signal terminals (terminals 43b connected to the substrate 413 through the wire bond 47, Fig. 4) is coupled to the power circuit with a bond wire.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jojima (US 20190245443), in view of Matsumoto (US 20210091119).
Regarding claim 4, Jojima discloses the claimed invention as set forth in claim 1.
Jojima does not explicitly disclose a plurality of signal terminals that provide a plurality of control signals for the power circuit, wherein portions of the plurality of signal terminals extend out of a second side of the housing that is opposite the first side of the housing.
Matsumoto suggests a plurality of signal terminals that provide a plurality of control signals (HINU, HINV, HINW; Fig. 9) for the power circuit, wherein portions of the plurality of signal terminals extend out of a second side (the opposite side to the input/output side having input P, outputs U, V, and W) of the housing that is opposite the first side of the housing.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include the signal terminal in order to transmit the control signal to the device.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jojima (US 20190245443), in view of Leiri (US 20210167003).
Regarding claim 6, Jojima discloses the claimed invention as set forth in claim 1.
Jojima does not explicitly disclose each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin head and a second pin head that is staggered apart from the first pin head.
Leiri suggests the pins (P1 – P3, Q1G, Q2G, Q3G) are staggered from each other, Fig. 1.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the pins in order to adapt to the footprint of other electronic part that connected to the pins.
Claim(s) 11, 15, 16, 21 - 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jojima (US 20190245443), in view of Matsumoto (US 20210091119), in further view of Leiri (US 20210167003).
Regarding claim 11, Jojima discloses a device package comprising:
a plurality of power devices (the power converter 10, Fig 8) arranged to provide a power circuit having a first input (input connected to terminal 54), a second input (the input connected to terminal 55), and at least one output (the output 52);
a housing (the case 70) for the plurality of power devices and portions of the plurality of signal terminals; wherein
Jojima does not explicitly disclose a plurality of signal terminals that provide a plurality of control signals for the power circuit; and pin heads of adjacent pairs of the plurality of signal terminals are staggered apart from one another.
Matsumoto suggests a plurality of signal terminals that provide a plurality of control signals (HINU, HINV, HINW; Fig. 9) for the power circuit.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include the signal terminal in order to transmit the control signal to the device.
Leiri suggests the pins (P1 – P3, Q1G, Q2G, Q3G) are staggered from each other, Fig. 1.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the pins in order to adapt to the footprint of other electronic part that connected to the pins.
Regarding claim 15, Jojima discloses the claimed invention as set forth in claim 11. Jojima further suggests at least one first input power terminal (54) providing a first input for the power circuit; at least one second input power terminal (55) providing a second input for the power circuit; and at least one output power terminal (52a – 52c) providing at least one output for the power circuit.
Regarding claim 16, Jojima discloses a device package comprising:
a plurality of power devices (power converter 10, Fig. 8) arranged to provide a power circuit having a first input (the input circuit connected to the terminal 54), a second input (the input circuit connected to the terminal 55), and at least one output (the output circuit 52);
a housing (the case 70) for the plurality of power devices and portions of the plurality of signal terminals, the housing having a top side (left side; Fig. 9), a bottom side (right side, Fig. 10) opposite the top side, and a first side (the side between the left side and the right side) extending from the top side to the bottom side, the top side having a greater surface area relative to the first side;
Jojima does not explicitly disclose a plurality of signal terminals that provide a plurality of control signals for the power circuit; and wherein portions of the plurality of signal terminals extend out of a second side of the housing that is opposite the first side of the housing, wherein at least one of the plurality of signal terminals extends a first distance from the second side of the housing and at least one of the plurality of signal terminals extends a second distance from the second side of the housing, the second distance being different from the first distance.
Matsumoto suggests a plurality of signal terminals that provide a plurality of control signals (HINU, HINV, HINW; Fig. 9) for the power circuit.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include the signal terminal in order to transmit the control signal to the device.
Leiri suggests the pins (P1 – P3, Q1G, Q2G, Q3G) are staggered from each other, Fig. 1.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the pins in order to adapt to the footprint of other electronic part that connected to the pins.
Regarding claim 21, Jojima discloses the claimed invention as set forth in claim 16. Matsumoto further suggests each signal terminal of the plurality of signal terminals extends from the second side of the housing (the opposite side to the input/output side having input P, outputs U, V, and W).
Regarding claim 22, Jojima discloses the claimed invention as set forth in claim 16. Jojima further suggests at least one of the first input (54), the second input (55), and the at least one output (52 – 52c) of the power circuit extend from the first side of the housing (all these terminals extend on the same side).
Regarding claim 23, Jojima discloses the claimed invention as set forth in claim 22. Jojima further suggests each of the first input (54), the second input (55), and the at least one output (52a – 52c) of the power circuit extend from the first side of the housing.
Allowable Subject Matter
Claims 2, 5, 12 – 14, 17 - 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 2, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the at least one first input power terminal comprises a first V- terminal and a second V- terminal extending out of the first side of the housing and the at least one second input power terminal comprises a first V+ terminal and a second V+ terminal extending out of the first side of the housing. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 5, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 4, a combination of limitations that a substrate comprising at least one jumper pad, a first bond wire, and a second bond wire; and the first bond wire extends from at least one of the plurality of signal terminals to the at least one jumper pad, and the second bond wire extends from the at least one jumper pad to the power circuit. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 12, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 11, a combination of limitations that the plurality of signal terminals comprises a first plurality of gate signal terminals that provide gate control signals to gates of a first set of the plurality of power devices and a second plurality of gate signal terminals that provide gate control signals to gates of a second set of the plurality of power devices. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 16, a combination of limitations that the plurality of signal terminals comprises a first plurality of gate signal terminals that provide gate control signals to gates of a first set of the plurality of power devices and a second plurality of gate signal terminals that provide gate control signals to gates of a second set of the plurality of power devices. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamane (US 20020054473) discloses a power device, Fig. 2, having input 10, outputs 12 on the same side.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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