DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McElrea et al. (U.S. Patent No. 7,923,349).
Regarding to claim 8, McElrea teaches a method of forming a substrate with one or more semiconductor die, the method comprising (the method steps are not claimed to impart in a specific order):
forming a plurality of semiconductor devices across a first surface of a semiconductor wafer (Figs. 2A-B, forming plurality of semiconductor devices 21 across a first surface of a semiconductor wafer);
applying a metal layer on a second surface of the semiconductor wafer (Fig. 2B, element 16);
applying a passivation layer over the plurality of semiconductor devices and the first surface of the semiconductor wafer (Fig. 8, element 82);
etching the metal layer to form a patterned array of the metal layer and an array of die streets exposing portions of the semiconductor wafer (Fig. 9, etching the metal layer through layers 62/16/90);
partially etching the semiconductor wafer exposed in the array of die streets starting from the second surface of the semiconductor wafer toward the passivation layer (Fig. 9, partially etching the semiconductor wafer exposed in the array of die streets starting from the second surface of the semiconductor wafer toward the passivation layer); and
ablating away any remaining material of the semiconductor wafer and passivation layer within the array of die streets to separate the substrate with one or more semiconductor die from the semiconductor wafer (Fig. 25, column 9, lines 40-47, any remaining material of the semiconductor wafer and passivation layer within the array of die streets are removed to separate the substrate with one or more semiconductor die from the semiconductor wafer).
Regarding to claim 2, McElrea teaches any remaining material of the semiconductor wafer and passivation layer within the array of die streets to separate the substrate with one or more semiconductor die from the semiconductor wafer (tape is material to protect the one or more semiconductor die from contaminants).
Regarding to claim 3, McElrea teaches the passivation layer is a non-plasma etchable layer (tape can be etched without plasma, such as a wet etch).
Regarding to claim 5, McElrea teaches partially etching the semiconductor wafer comprises only partially etching the semiconductor wafer (part of the semiconductor wafer is removed in middle of etching process, before the etching process continues to complete dicing).
Regarding to claim 6, McElrea teaches fully etching the semiconductor wafer (Fig. 10, wafer 90 is fully etched).
Claims 8-10, 12, 14-16, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (U.S. Patent Application Publication No. 2008/0242052).
Regarding to claim 8, Feng teaches a method of forming one or more semiconductor die, the method comprising (the method steps are not claimed to impart in a specific order):
forming an array of semiconductor devices distributed across a first surface of a semiconductor substrate (Fig. 1, Ia-IIa, array of semiconductor devices distributed across a first surface of a semiconductor substrate 10);
forming an edge ring on a second surface of the semiconductor substrate (Fig. 1, IIIa, forming edge ring 78 on a second surface of the semiconductor substrate);
patterning a metal array on a portion of the second surface of the semiconductor substrate, wherein the semiconductor substrate is exposed at a plurality of die streets (Fig. 1, VIIa-VIIIa, patterning metal array 18 on a portion of the second surface of the semiconductor substrate, wherein the semiconductor substrate is exposed at a plurality of die streets);
forming a passivation layer over the first surface of the semiconductor substrate including the array of semiconductor devices (Fig. 1, IIIa-IVa, passivation layer 19 formed over the first surface of the semiconductor substrate including the array of semiconductor devices); and
singulating the one or more semiconductor die by ablating away the semiconductor substrate, the passivation layer, and metal structures within the plurality of die streets (Fig. 1, IVa, VIIIa, singulating the semiconductor die 30 by ablating away (removal) the semiconductor substrate, the passivation layer, and metal structures within the plurality of die streets 28).
Regarding to claim 9, Feng teaches the passivation layer comprises one or more of a silicon nitride, oxide, metal electrical test structure, electrical test pad, silicon dioxide, polyimide, metal pad, under bump metallization, or any other material configured to one of facilitate thermal connection between the one or more semiconductor die or protect the one or more semiconductor die from contaminants ([0059], lines 2-3, tape is material to protect the one or more semiconductor die from contaminants).
Regarding to claim 10, Feng teaches the passivation layer is a non-plasma etchable layer (tape can be etched without plasma, such as a wet etch).
Regarding to claim 12, Feng teaches the semiconductor substrate is less than 50 microns thick ([0066], lines 10-12, 1 mil =1/1000 inch = 25 microns).
Regarding to claim 14, Feng teaches a method of forming one or more semiconductor die, the method comprising (the method steps are not claimed to impart in a specific order):
thinning a portion of a semiconductor wafer at a second surface of the semiconductor wafer to form an edge ring on the second surface of the semiconductor wafer (Fig. 1, IIIa, thinning a portion of a semiconductor wafer 10 at a second surface of the semiconductor wafer to form an edge ring on the second surface of the semiconductor wafer);
patterning a metal array along a plurality of die streets on a thinned portion of the second surface of the semiconductor wafer to expose a portion of the semiconductor wafer in the plurality of die streets (Fig. 1, VIIa-VIIIa, patterning metal array along a plurality of die streets on a thinned portion of the second surface of the semiconductor wafer to expose a portion of the semiconductor wafer in the plurality of die streets);
forming a plurality of semiconductor devices one of on or within a first surface of the semiconductor wafer (Fig. 1, IIa);
applying a passivation layer over the plurality of semiconductor devices (Fig. 1, IIIa, element 19);
etching the semiconductor wafer exposed in the plurality of die streets at least partially toward the passivation layer (Fig. 1, VIIa); and
singulating the one or more semiconductor die by ablating away the passivation layer within the plurality of die streets ([0064], lines 9-12, singulating the semiconductor die 30 by ablating away (removal) the semiconductor substrate and the passivation layer within the plurality of die streets 28).
Regarding to claim 15, Feng teaches the passivation layer comprises one or more of a silicon nitride, oxide, metal electrical test structure, electrical test pad, silicon dioxide, polyimide, metal pad, under bump metallization, or any other material configured to one of facilitate thermal connection between the one or more semiconductor die or protect the one or more semiconductor die from contaminants ([0059], lines 2-3, tape is material to protect the one or more semiconductor die from contaminants).
Regarding to claim 16, Feng teaches the passivation layer is a non-plasma etchable layer (tape can be etched without plasma, such as a wet etch).
Regarding to claim 18, Feng teaches the portion of the semiconductor wafer is thinned to less than 50 microns thick ([0058], lines 11-13), 1 mil =1/1000 inch = 25 microns).
Regarding to claim 20, Feng teaches a portion of the semiconductor wafer is ablated away with the passivation layer (Fig. 1, VIIIa).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over McElrea et al. (U.S. Patent No. 7,923,349), as applied to claim 1 above, in view of Lei et al. (U.S. Patent No. 9,209,084).
Regarding to claim 7, McElrea does not disclose a plurality of test structures within the array of die streets. Lei teaches a plurality of test structures within the array of die streets (column 8, lines 15-17). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified McElrea in view of Lei to configure a plurality of test structures within the array of die streets in order to perform in-line tests during the fabrication process, thus to increase process yield.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (U.S. Patent Application Publication No. 2008/0242052), as applied to claim 8 above.
Regarding to claim 13, Feng teaches the semiconductor substrate is 2-4 mils thick ([0058], lines 11-13). Feng does not disclose the semiconductor substrate is less than 25 microns thick, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the semiconductor substrate to be less than 25 microns thick in order to reduce stress, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (U.S. Patent Application Publication No. 2008/0242052), as applied to claim 8 above.
Regarding to claim 19, Feng teaches the portion of the semiconductor wafer is thinned to 2-4 mils thick ([0058], lines 11-13). Feng does not disclose the portion of the semiconductor wafer is thinned to less than 25 microns thick, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to thin the semiconductor substrate to be less than 25 microns thick in order to reduce stress, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 4, 11, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 4, the prior art fails to anticipate or render obvious the claimed limitations including “the passivation layer is configured to facilitate electrical connection between the one or more semiconductor die” in combination with the limitations recited in claim 1.
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “the passivation layer is configured to facilitate electrical connection between the one or more semiconductor die” in combination with the limitations recited in claim 8.
Regarding to claim 17, the prior art fails to anticipate or render obvious the claimed limitations including “the passivation layer is configured to facilitate electrical connection between the one or more semiconductor die” in combination with the limitations recited in claim 14.
Pertinent Art
For the benefits of the Applicant, US-7982279-B2, US-7078266-B2, and US-6908784-B1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The cited references fail to disclose “etching the metal layer to form a patterned array of the metal layer and an array of die streets exposing portions of the semiconductor wafer, partially etching the semiconductor wafer exposed in the array of die streets starting from the second surface of the semiconductor wafer toward the passivation layer.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Vu A Vu whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
