DETAILED ACTION
Claims 1-18 and 20 are pending.
Claims 4-5, 9, 13-14, 18, and 20 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
As set forth in the previous Office Action, this application contains claims directed to the following patentably distinct species:
Setting a hardware indicator (e.g. in a bitfield) for each load suboperation (FIG.4).
Incrementing a counter for each load suboperation (FIG.5).
Applicant initially elected species I without traverse. However, after the elected species was rejected by the prior art, applicant has shifted to claim the non-elected species (in new claim 20) while traversing the original restriction requirement.
Per MPEP 819, “[t]he general policy of the Office is that applicants are not permitted to shift to claim another invention after an election is made and an Office action on the merits is made on the elected invention. Specifically, the applicant may not disaffirm or change their election, as a matter of right, after making an oral election and receiving an Office action based upon that oral election in a pending application. See 37 CFR 1.142(b). In addition, the applicant cannot, as a matter of right, file a request for continued examination (RCE) on claims that are independent and distinct from the claims previously claimed and examined (i.e., applicant cannot switch inventions by way of an RCE as a matter of right). See MPEP § 706.07(h), subsection VI.(B). When claims are presented which the examiner finds are drawn to an invention other than the one elected, he or she should treat the claims as outlined in MPEP § 821.03.”
According to MPEP 821.03 and 37 CFR 1.145, “[i]f, after an office action on an application, the applicant presents claims directed to an invention distinct from and independent of the invention previously claimed, the applicant will be required to restrict the claims to the invention previously claimed…”. Accordingly, claim 20 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b).
On page 12 of applicant’s response, applicant argues that “the bitfield species and counter species are not mutually exclusive, they are capable of being used together, and do not have a materially different effect. Thus, under MPEP 806.05(j), the bitfield species and counter species do not have two-way distinctiveness. Accordingly, under MPEP 806.04(b), restriction between the bitfield species and the counter species is improper and should not be required.”
This is not persuasive because:
The species are mutually exclusive. From MPEP 806.04(f), “[c]laims to different species are mutually exclusive if one claim recites limitations disclosed for a first species but not a second, while a second claim recites limitations disclosed only for the second species and not the first. This may also be expressed by saying that to require restriction between claims limited to species, the claims must not overlap in scope.” Clearly, claims for species I and II do not overlap in scope and each claim does not include limitations of the other species.
There is no evidence, but instead a mere unsupported assertion by applicant, that the species are capable of use together. The disclosure would appear to support the opposite because the bitfield and counter are two different means to the same end. That is, if the system is using a bitfield to track how many load suboperations have occurred for a given gather, why would the system also use a counter to track how many load suboperations have occurred for the given gather? Using one alone is sufficient for tracking. Using the second for the same gather would introduce redundancy and lower efficiency (since more power would be consumed to operate the second for no additional information). Thus, one of ordinary skill in the art would generally understand that one (not both) would be implemented together for a given gather.
From MPEP 802.01(II), “[r]elated inventions are distinct if the inventions as claimed are not connected in at least one of design, operation, or effect”, and, from MPEP 806.05(j), “the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect.” Because the species are not usable together, consideration of different design, mode of operation, function, or effect is unnecessary. However, assuming arguendo that the species are capable of use together, the additional considerations are alternatives (“can have a materially different design, mode of operation, function, or effect.”). Even if applicant believes the species have the same effect, the examiner asserts that they have different designs (bit field/mask versus incrementing/decrementing counter), and mode of operation (one includes a group of individually-settable bits, while the other counts up and down to represent sequentially numbers, and generates carry bits (as counting does)). Note that if the species can be concluded to have a different design, mode of operation, function, or effect, the capability (or incapability) of use together is not a necessary consideration.
Thus, since applicant has not stated that the species in question are obvious variants, the
related species are distinct according to (A), (B), and (C) in MPEP 806.05(j). Thus, the restriction requirement is still deemed proper and is therefore made FINAL.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 25, please confirm that “For each gather operation, the load suboperation knows (3) how many load suboperations there are for the particular gather operation” is correct. The examiner does not understand why any given load suboperation needs to know about another load suboperation, let alone the total number of load suboperations. Applicant has not argued this objection and, thus, it is maintained.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12 and 15-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 10, lines 10 and 13, both instances of “the one register file entry”, which could refer to the entry of line 1, or to the entry of line 9.
In claims 11-12, 15, and 17, each instance of “the one register file entry” for similar reasoning.
Claims 11-12 and 15-17 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 10-12, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ould-Ahmed-Vall et al. (US 2014/0201498 A1) (herein referred to as OAV).
Referring to claim 1, OAV has taught a method for performing a gather operation using one register file entry as a destination for all load suboperations of the gather operation (FIG.15), the method comprising:
detecting a gather operation (FIG.15, 1505) comprising a plurality of load suboperations accessing independent memory locations (from FIG.15, step 1530 is performed multiple times, one for each load suboperation that accesses a memory location based on its index);
performing the plurality of load suboperations (FIG.15, step 1530), each of the plurality of load suboperations writing to a different portion of the one register file entry without overwriting the other portions of the one register file entry (FIG.15, 1535);
determining that all of the plurality of load suboperations have been completed (FIG.15, 1550); and
upon determining that all of the plurality of load suboperations have been completed, making the one register file entry available for a read operation (from FIG.15, steps 1550-1565, when it is determined that all of the load sub-operations have written their data into the result register (register file entry), e.g. Vmm1 in paragraph 91, Vmm1 is made available for reading so that the subsequent operation (op) can be performed).
Referring to claim 2, OAV has taught the method of claim 1, wherein performing the plurality of load suboperations comprises, for each load suboperation of the plurality of load suboperations, setting a hardware indicator for the portion of the one register file entry that has been written to by the respective load suboperation (FIG.1540), and wherein determining that all of the plurality of load suboperations have been completed comprises determining that the hardware indicators for all portions of the one register file entry have been set (FIG.15, 1540, and paragraph 138).
Referring to claim 3, OAV has taught the method of claim 2, wherein setting the hardware indicator for the portion of the one register file entry that has been written to by the respective load suboperation comprises setting a bit in a bitfield for each portion of the one register file entry that has been written to by the respective load suboperation (FIG.15, 1540, where each mask field includes a bit of an overall mask (bitfield)).
Referring to claim 6, OAV has taught the method of claim 1, wherein the plurality of load suboperations accessing independent memory locations will not completely fill the one register file entry (from FIG.15, the load suboperations are only the ones have a corresponding mask bit set to a first value (steps 1520-1530). When the number of mask bits equal to a first value is less than the total number of mask buts, the plurality of load suboperations will not fill up the register).
Referring to claim 7, OAV has taught the method of claim 1, wherein performing the plurality of load suboperations comprises performing the plurality of load suboperations in any order (from FIG.15, one mask field is read at a time to perform one load suboperation at a time. This defines an order for the load suboperations. Thus, where all mask fields have the first value, load operations 1 through 8 would be performed in that order, which is an order covered by the claim).
Referring to claim 8, OAV has taught the method of claim 1, wherein the one register file entry comprises a vector register file entry (from paragraph 136, the register file entry is a vector register).
Claim 10 is mostly rejected for similar reasoning as claim 1. OAV has further taught a register file a plurality of register file entries (paragraphs 89-90 refer to multiple vector registers, which would make up a vector register file. This file would include at least Vmm1 and Vmm2 as shown in paragraph 91); and processing circuitry configured to perform the claimed steps (processor circuitry including execution units (abstract), instruction decoder (paragraph 136), etc., carry out the claimed steps).
Claims 11-12 and 15-17 are rejected for similar reasoning as claims 2-3 and 6-8, respectively.
Response to Arguments
On pages 13-14 of applicant’s response, applicant argues that OAV fails to disclose “each of the plurality of load suboperations writing to a different portion of the one register file entry without overwriting the other portions of the one register file entry”. Specifically, applicant argues that OAV does not explicitly state that the corresponding data elements are gathered from memory and stored in the same vector register as the other data elements. Applicant emphasizes OAV, step 1570, and paragraph 135, which set forth that the results of the SIMD gather-op instruction are stored in a vector register, and that this step would not be necessary if the gathered data elements were already stored in the same vector register.
The examiner respectfully disagrees. The storage into the same destination register occurs in step 1535. This is the part being relied on for rejection of the load suboperations. After all of the loading is done (step 1550), a second operation is performed on the loaded elements in the destination register and a new result is stored in the destination register. Looking at paragraph 91, a gather of elements occurs into a single destination register Vmm1, which is a packed register with a plurality of fields (e.g. paragraphs 4 and 136). In other words, each load suboperation will load data into a respective field of Vmm1 (this is the claimed writing to a different portion of one register file entry without overwriting other portions). The idea is to fill a register with multiple elements and then perform an additional operation on them in parallel (this corresponds to the “op” portion of “gather-op”). As a very basic example, assume someone wants to logically-AND four values with four elements in memory. A gather-AND could be performed to load the four elements from memory into different fields of Vmm1 to obtain Vmm1 = |A|B|C|D|. Then, where Vmm2 = |E|F|G|H|, i.e., the four values (EFGH) to be ANDed, the result of gather-AND would be Vmm1 = |(A AND E)|(B AND F)|(C AND G)|(D AND H)|.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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