DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/29/2025 have been considered by the Examiner.
Claim Objections
Claim(s) 4 and 16 are objected to because of the following informalities:
Claim 4 recites a term “first probe” in line 2. Examiner suggests amending the term to recite “the first probe” to restore clarity.
Claim 16 recites a term “a first probe” in line 2. Examiner suggests amending the term to recite “the first probe” to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 4, 6, 16 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. The rationale for this finding is explained below:
Claim(s) 4 and 16 recite an element "the fourth probe” in the last line before introduction. There is insufficient antecedent basis for this element in the claim(s).
Claim(s) 6 and 19 recite an element "the current” in line 1 before introduction. There is insufficient antecedent basis for this element in the claim(s).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 9-13, 15-17 and 22 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Mikkola et al. (US 20160161548; hereinafter Mikkola).
Regarding claim 1, Mikkola discloses in figure(s) 1-25 a system for electrical characterization of a logical cell, the system comprising:
a plurality of probes (434; fig. 24);
control circuitry (437), electrically coupled with the probes;
bias circuitry, electrically coupled with one or more of the probes and configured to apply a bias voltage to the one or more probes (para. 10 - remotely configurable test structure that can be programmed with varying bias conditions for testing of process variation or numerous failure modes on large sample sizes; para. 12 - controlling DUT switch block stress switches to selectively apply bias from off-chip analog sources to stress one or more groups of test devices; para. 46 - a programmable controller for generation of the bias voltages and currents programmable voltage and current sources); and
one or more machine-readable storage media, electronically coupled with the control circuitry (para. 51 - host controller and benchtop tester may also write information to the memory to specify test information such as tests completed and DUTs tested), the media storing instructions that, when executed by a machine, cause the machine to perform operations comprising:
landing the probes (434; fig. 24) on a surface of an integrated circuit (dut 202; fig. 24), thereby electrically coupling the probes with the logical cell, comprising a plurality of electrically coupled transistors (86; fig. 5b; para. 25 - probing may comprise or support automated measurement or detection of one or more characteristics of the sample(s). include IC, transistor), the logical cell having been electrically isolated from one or more conductive structures of the integrated circuit (para. 56 - Each cell 84 is connected to a different DUT 86; clm. 2 - DUTs are independent of each other);
applying one or more bias voltages to the logical cell via one or more of the probes, using the bias circuitry (para. 56 - binary value in S sub-cell 88a is coupled to the control input of the stress switch in each of the one or more switch blocks; para. 66 - STRESS switches 134 are closed and thus the DUT is in stress mode, i.e. receiving stress bias voltages or currents from the benchtop tester; figs. 5a, 9a);
performing an operational test (benchtop tester; fig. 3) of the logical cell using the probes, wherein the plurality of transistors together defines an arrangement configured to generate an output voltage (para. 53 - an output interface (e.g. socket or contact pads) that mates with the pin out of a particular test chip) representative of one or more logical states of the logical cell in response to one or more input voltage signals (para. 59 - shift and load functions may be controlled by a single pin where one logic state (for example “0”) indicates a shift operation and the other logic state (for example “1”) indicates a load operation; para. 64 - OFF state ensures that no stresses are accidentally applied to the devices and that the terminals are not floating during their non-operational period), the operational test being based at least in part on the arrangement (para. 13 - an adaptor having an input interface that mates with the universal interface and an output interface that mates with the common sets of contacts on the test structure, and one or more controllers responsive to the selected test modes and specified test conditions to program the sources and to control the addressing circuit to applying a sequence of digital measurement selection commands to the test structure; para. 46 - Tester includes an adapter having an input interface that mates with a universal benchtop interface and an output interface that mates with the test chip); and
generating output data describing the one or more logical states of the logical cell over at least a portion of the operational test (DUT register shift, output in figs. 7b,8; para. 63 – dut control logic 116 truth table; analog signals 193,197 in fig. 9a and para. 52 - main card also includes an analog-to-digital (ADC) converter to convert measurement signals to digital data; para. 108 - after probe test the wafer is diced and only the good dies are packed).
Regarding claim 3, Mikkola discloses in figure(s) 1-25 the system of claim 1, wherein landing the probes comprises electrically coupling a first probe with a transistor gate of the logical cell and a second probe with an output terminal of the logical cell (para. 27-28 - DUT including a pMOS transistor with four switch blocks coupled to its G, D, S and body terminals under stress and measurement bias conditions, respectively; figs. 7, 9-10).
Regarding claim 4, Mikkola discloses in figure(s) 1-25 the system of claim 3, wherein performing the operational test of the logical cell comprises coupling a test signal into the logical cell via first probe, and wherein generating the output data comprises coupling a voltage signal out of the logical cell from the fourth probe (para. 98 - a DUT structure is shown with 6 terminals representing a general transistor 200 with its base 4 terminals 201 (Gate, Drain, Body and Source) and 2 sense terminals (Sense_Drain and Sense_Source); clm. 12 - commands to open the stress switches and close the measurement switches; fig. 16).
Regarding claim 9, Mikkola discloses in figure(s) 1-25 the system of claim 1, wherein the surface of the integrated circuit corresponds to a metallization layer (206; fig. 16) of the integrated circuit, Mn, and wherein the integrated circuit (202) defines a trench in the metallization layer Mn at least partially surrounding the logical cell (200).
Regarding claim 10, Mikkola discloses in figure(s) 1-25 the system of claim 9, wherein the trench is formed through a subordinate layer, Mm, below the metal layer Mn. Nets (para. 49 - PMOS transistors, NMOS transistors and vias used to conduct current between different metal layers in an IC may be formed into three separate arrays. Each of these may be further separated into additional arrays for testing different failure modes or for different geometries of the test devices).
Regarding claim 11, Mikkola discloses in figure(s) 1-25 the system of claim 1, wherein the conductive structures comprise power distribution nets (para. 52 - a test chip supply 54 to provide power to the test chip and addressing control 56 to format the addressing selection commands for the test chip; para. 76 - eaters are parallel connected similar to the corresponding DUT array, each heater array having its own heater VDD and VSS pins; figs. 4,15).
Regarding claim 12, Mikkola discloses in figure(s) 1-25 the system of claim 1, wherein a probe of the plurality of probes is coupled with a circuit element configured to improve a quality of an alternating current signal coupled into the logical cell via the probe (para. 12 - characterizing IC fabrication process comprises providing a test structure, connecting off-chip analog current or voltage sources and analog current or voltage meters to one or more of the measurement contacts of the structure).
Regarding claim 13, Mikkola discloses in figure(s) 1-25 a method for electrical characterization of a logical cell, the method comprising:
landing a plurality of probes (434; fig. 24) on a surface of an integrated circuit (dut 202; fig. 24), thereby electrically coupling the probes with the logical cell (120; fig. 9a), comprising a plurality of electrically coupled transistors (110,112; fig. 7b), the logical cell having been electrically isolated from one or more conductive structures of the integrated circuit (para. 98 - DUT structures are organized in a matrix type of structure … DUT structure 202 is comprised of a DUT 200 surrounded by contact points (probe pads) 203 and interconnects 204 between the DUT itself and the probe pads);
applying one or more bias voltages to the logical cell via one or more of the probes, using bias circuitry, the bias circuitry being configured to apply a bias voltage to the one or more probes (para. 56 - binary value in S sub-cell 88a is coupled to the control input of the stress switch in each of the one or more switch blocks; para. 66 - STRESS switches 134 are closed and thus the DUT is in stress mode, i.e. receiving stress bias voltages or currents from the benchtop tester; figs. 5a, 9a);
performing an operational test (benchtop tester; fig. 3) of the logical cell using the probes, wherein the plurality of transistors together defines an arrangement configured to generate an output voltage (para. 53 - an output interface (e.g. socket or contact pads) that mates with the pin out of a particular test chip) representative of one or more logical states of the logical cell in response to one or more input voltage signals (para. 59 - shift and load functions may be controlled by a single pin where one logic state (for example “0”) indicates a shift operation and the other logic state (for example “1”) indicates a load operation; para. 64 - OFF state ensures that no stresses are accidentally applied to the devices and that the terminals are not floating during their non-operational period), the operational test being based at least in part on the arrangement (para. 13 - an adaptor having an input interface that mates with the universal interface and an output interface that mates with the common sets of contacts on the test structure, and one or more controllers responsive to the selected test modes and specified test conditions to program the sources and to control the addressing circuit to applying a sequence of digital measurement selection commands to the test structure; para. 46 - Tester includes an adapter having an input interface that mates with a universal benchtop interface and an output interface that mates with the test chip); and
generating output data describing the one or more logical states of the logical cell over at least a portion of the operational test (DUT register shift, output in figs. 7b,8; para. 63 – dut control logic 116 truth table; analog signals 193,197 in fig. 9a and para. 52 - main card also includes an analog-to-digital (ADC) converter to convert measurement signals to digital data; para. 108 - after probe test the wafer is diced and only the good dies are packed).
Regarding claim 15, Mikkola discloses in figure(s) 1-25 the method of claim 13, wherein landing the probes comprises electrically coupling a first probe with a transistor gate of the logical cell and a second probe with an output terminal of the logical cell (para. 27-28 - DUT including a pMOS transistor with four switch blocks coupled to its G, D, S and body terminals under stress and measurement bias conditions, respectively; figs. 7, 9-10).
Regarding claim 16, Mikkola discloses in figure(s) 1-25 the method of claim 15, wherein performing the operational test of the logical cell comprises coupling a test signal into the logical cell via a first probe, and wherein generating the output data comprises coupling an output signal out of the logical cell from the fourth probe (para. 98 - a DUT structure is shown with 6 terminals representing a general transistor 200 with its base 4 terminals 201 (Gate, Drain, Body and Source) and 2 sense terminals (Sense_Drain and Sense_Source); clm. 12 - commands to open the stress switches and close the measurement switches; fig. 16).
Regarding claim 17, Mikkola discloses in figure(s) 1-25 the method of claim 15, wherein the second probe is coupled with a load, and wherein the method comprises measuring a voltage across the load (para. 12 - voltage meters to one or more of the measurement contacts of the structure).
Regarding claim 22, Mikkola discloses in figure(s) 1-25 the method of claim 13, wherein the surface of the integrated circuit corresponds to a metallization layer (206; fig. 16) of the integrated circuit, Mn, and wherein the integrated circuit (202) defines a trench in the metallization layer Mn at least partially surrounding the logical cell (200).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Mikkola in view of Or-Bach et al. (US 8058137).
Regarding claim(s) 2 and 14, Mikkola teaches in figure(s) 1-25 the system of claim 1 and the method of claim 13, respectively,
Mikkola does not teach explicitly wherein landing the probes comprises: electrically coupling a first probe with a positive supply input of the logical cell; and electrically coupling a second probe with a negative supply input of the logical cell, wherein applying the bias voltages comprises coupling a positive bias voltage into the first probe and coupling a negative bias voltage into the second probe.
However, Or-Bach teaches in figure(s) 17-18 wherein landing the probes comprises: electrically coupling a first probe (probe 17D08, 1726; figs. 17B,17D) with a positive supply input (Vbb+; fig. 17B) of the logical cell (1734, 1732; 1808, 1806; figs. 17B, 18); and electrically coupling a second probe (probe 17D08, 1725; figs. 17B, 17D) with a negative supply input (Vbb-; fig. 17B) of the logical cell (1734, 1732; 1808, 1806; figs. 17B, 18), wherein applying the bias voltages comprises coupling a positive bias voltage into the first probe (1726, 17D08) and coupling a negative bias voltage into the second probe (1725, 17D08).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Mikkola by having wherein landing the probes comprises: electrically coupling a first probe with a positive supply input of the logical cell; and electrically coupling a second probe with a negative supply input of the logical cell, wherein applying the bias voltages comprises coupling a positive bias voltage into the first probe and coupling a negative bias voltage into the second probe as taught by Or-Bach in order to provide "foundation-located back bias could also be used to minimize leakage due to process variation" (col. 18 lines 60-65).
Claim(s) 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mikkola in view of WATANABE et al. (US 20130106450).
Regarding claim(s) 5 and 18, Mikkola teaches in figure(s) 1-25 the system of claim 1 and the method of claim 13, respectively,
Mikkola does not teach explicitly wherein the output data comprise voltage data, for which a positive value of the voltage corresponds to a first logical state of the logical cell under test, and wherein a negative value of the voltage corresponds to a second logical state of the logical cell under test.
However, WATANABE teaches in figure(s) 1-3 wherein the output data (output 62; figs. 1-2) comprise voltage data, for which a positive value of the voltage corresponds to a first logical state of the logical cell under test, and wherein a negative value of the voltage corresponds to a second logical state of the logical cell under test (24; fig. 1; para. 49 - output signal whose voltage varies between an L-logic voltage and an H-logic voltage according to the variation in the logic of the input signal).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Mikkola by having wherein the output data comprise voltage data, for which a positive value of the voltage corresponds to a first logical state of the logical cell under test, and wherein a negative value of the voltage corresponds to a second logical state of the logical cell under test as taught by WATANABE in order to provide "A drive circuit for outputting an output signal having a voltage determined by a logic of an input signal includes a constant voltage generating section generating a constant bias voltage" (abstract).
Allowable Subject Matter
Claim(s) 7-8 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim(s) 7 and 20, the prior arts of record do not fairly teach or suggest “wherein the arrangement defines a flip-flop, wherein the plurality of probes comprises eight or more probes, and wherein landing the probes comprises: coupling a first probe with a positive supply input of the logical cell; coupling a second probe with a negative supply input of the logical cell; coupling a third probe with a test signal input, “D,” of the logical cell; coupling a fourth probe with a clock signal input of the logical cell; and coupling a fifth probe with a voltage output of the logical cell” including all of the limitations of the base claim and any intervening claims.
Claim(s) 8 and 21 are objected for dependent upon the objected base claim(s).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Daruwalla et al. (US 20220385240) discloses "Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit".
Segarra et al. (US 20220003812) discloses "A testing method and apparatus is disclosed for testing an integrated circuit device".
Kuenemund et al. (US 20150294944) discloses "A method for manufacturing a digital circuit is described comprising forming two field effect transistors, threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input has a predetermined defined logic state".
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
Prosecution Insights