DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,165,733. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, claim 1 of Pat. ‘733 discloses a sense amplifier, comprising: a sense amplifier circuit, including a first reference node and a second reference node, sensing a plurality of bit lines according to an enable signal; and a reference sharing circuit, coupled to the sense amplifier circuit, wherein the reference sharing circuit comprises: a plurality of first switches, coupled to the first reference node of the sense amplifier circuit, controlling a first electrical connection of a first reference signal according to a control signal, wherein the control signal is derived from the enable signal; and a plurality of second switches, coupled to the second reference node of the sense amplifier circuit, controlling a second electrical connection of a second reference signal according to the control signal.
Regarding claim 2, claim 2 of Pat. ‘733 discloses wherein when the control signal is in a first logic state, the plurality of first switches and the plurality of second switches are switched on to form the first electrical connection of the first reference signal and the second electrical connection of the second reference signal, and when the control signal is in a second logic state, the plurality of first switches and the plurality of second switches are switched off to break the first electrical connection of the first reference signal and the second electrical connection of the second reference signal.
Regarding claim 3, claim 3 of Pat. ‘733 discloses wherein the control signal is an inverted signal of the enable signal.
Regarding claim 4, claim 4 of Pat. ‘733 discloses wherein the plurality of first switches and the plurality of second switches are transistors of a same semiconductor type.
Regarding claim 5, claim 5 of Pat. ‘733 discloses wherein the plurality of bit lines include a first bit line and a second bit line, and the sense amplifier circuit comprises: a core sense circuit, coupled to the first bit line, pre-charging the first bit line to a target voltage in a pre-charge phase, sensing values from the first bit line in a first sensing phase, and sensing values from the second bit line in a second sensing phase; and a bit line pre-charge branch circuit, coupled to the second bit line, pre-charging the second bit line to the target voltage in the pre-charge phase, wherein the pre-charge phase is performed prior to the first sensing phase and the second sensing phase.
Regarding claim 6, claim 6 of Pat. ‘733 discloses wherein the plurality of first switches and the plurality of second switches are switched off during the pre-charge phase.
Regarding claim 7, claim 7 of Pat. ‘733 discloses wherein each of the first phase and the second phase includes a first sub-phase during which the enable signal is in the second logic state and a second sub-phase during which the enable signal is in the first logic state, the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched on during the first sub-phase, and the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched off during the second sub-phase.
Regarding claim 8, claim 8 of Pat. ‘733 discloses wherein the first reference node supplies the first reference signal for sensing a first logic value from the plurality of bit lines, and the second reference node supplies the second reference signal for sensing a second logic value from the plurality of bit lines.
Regarding claim 9, claim 9 of Pat. ‘733 discloses a memory device, comprising: a memory array, including a plurality of memory cells; a sense amplifier, coupled to the memory array through a plurality of bit lines, sensing values stored in the plurality of memory cells through the plurality of bit lines, wherein the sense amplifier comprises: a sense amplifier circuit, including a first reference node and a second reference node, sensing the plurality of bit lines according to an enable signal; and a reference sharing circuit, coupled to the sense amplifier circuit, wherein the reference sharing circuit comprises: a plurality of first switches, coupled to the first reference node of the sense amplifier circuit, controlling a first electrical connection of a first reference signal according to a control signal, wherein the control signal is derived from the enable signal; and a plurality of second switches, coupled to the second reference node of the sense amplifier circuit, controlling a second electrical connection of a second reference signal according to the control signal.
Regarding claim 10, claim 10 of Pat. ‘733 discloses wherein when the control signal is in a first logic state, the plurality of first switches and the plurality of second switches are switched on to form the first electrical connection of the first reference signal and the second electrical connection of the second reference signal, and when the control signal is in a second logic state, the plurality of first switches and the plurality of second switches are switched off to break the first electrical connection of the first reference signal and the second electrical connection of the second reference signal.
Regarding claim 11, claim 11 of Pat. ‘733 discloses wherein the control signal is an inverted signal of the enable signal.
Regarding claim 12, claim 12 of Pat. ‘733 discloses wherein the plurality of bit lines include a first bit line and a second bit line, and the sense amplifier circuit comprises: a core sense circuit, coupled to the first bit line, pre-charging the first bit line to a target voltage in a pre-charge phase, sensing values from the first bit line in a first sensing phase, and sensing values from the second bit line in a second sensing phase; and a bit line pre-charge branch circuit, coupled to the second bit line, pre-charging the second bit line to the target voltage in the pre-charge phase, wherein the pre-charge phase is performed prior to the first sensing phase and the second sensing phase.
Regarding claim 13, claim 13 of Pat. ‘733 discloses wherein the plurality of first switches and the plurality of second switches are switched off during the pre-charge phase.
Regarding claim 14, claim 14 of Pat. ‘733 discloses wherein each of the first phase and the second phase includes a first sub-phase during which the enable signal is in the second logic state and a second sub-phase during which the enable signal is in the first logic state, the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched on during the first sub-phase, and the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched off during the second sub-phase.
Regarding claim 15, claim 15 of Pat. ‘733 discloses wherein the first reference node supplies the first reference signal for sensing a first logic value from the plurality of bit lines, and the second reference node supply the second reference signal for sensing a second logic value from the plurality of bit lines.
Regarding claim 16, claim 16 of Pat. ‘733 discloses an operation method of a sense amplifier including a sense amplifier circuit and a reference sharing circuit, the reference sharing circuit is coupled to a first reference node and a second reference node of the sense amplifier circuit, the operation method comprising: receiving, by the sense amplifier circuit of the sense amplifier, an enable signal; receiving, by the reference sharing circuit of the sense amplifier, a control signal, wherein the control signal is derived from the enable signal; when the control signal is in a first logic state, switching on a plurality of first switches and a plurality of second switches to form a first electrical connection of a first reference signal and a second electrical connection of a second reference signal, wherein the plurality of first switches and the plurality of second switches are included in the reference sharing circuit; and when the control signal is in a second logic state, switching off the plurality of first switches and the plurality of second switches to break the first electrical connection of the first reference signal and the second electrical connection of the second reference signal.
Regarding claim 17, claim 17 of Pat. ‘733 discloses wherein the plurality of bit lines include a first bit line and a second bit line, and the method further comprising: pre-charging, by a core sense circuit of the sense amplifier circuit, the first bit line to a target voltage in a pre-charge phase; pre-charging, by a bit line pre-charge branch circuit of the sense amplifier circuit, the second bit line to the target voltage in the pre-charge phase; sensing values from the first bit line in a first sensing phase, and sensing values from the second bit line in a second sensing phase, wherein the pre-charge phase is performed prior to the first sensing phase and the second sensing phase.
Regarding claim 18, claim 18 of Pat. ‘733 discloses wherein the control signal is an inverted signal of the enable signal.
Regarding claim 19, claim 19 of Pat. ‘733 discloses wherein the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched off during the pre-charge phase.
Regarding claim 20, claim 20 of Pat. ‘733 discloses wherein each of the first phase and the second phase includes a first sub-phase during which the enable signal is in the second logic state and a second sub-phase during which the enable signal is in the first logic state, the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched on during the first sub-phase, and the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched off during the second sub-phase.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cha et al. (US Pub. 2017/0365308).
Regarding claim 1, Fig. 2 of Cha discloses a sense amplifier, comprising:
a sense amplifier circuit [BLSA], including a first reference node [N1] and a second reference node [N1, can be the same as first reference node], sensing a plurality of bit lines [BL1, BL2] according to an enable signal; and
a reference sharing circuit [combination of 130, and 150], coupled to the sense amplifier circuit [BLSA], wherein the reference sharing circuit comprises:
a plurality of first switches [one of switch 150, connects to VREF1], coupled to the first reference node [N1] of the sense amplifier circuit [BLSA], controlling a first electrical connection of a first reference signal [VREF1] according to a control signal [OSO3], wherein the control signal [IS03] is derived from the enable signal [any control signal that used to generated ISO3]; and
a plurality of second switches [other switch 150, paragraph 0029], coupled to the second reference node [N1] of the sense amplifier circuit [BLSA], controlling a second electrical connection [connection between VREF2 and N1] of a second reference signal [VREF2] according to the control signal [ISO3].
Regarding claims 2, 10, Fig. 2 of Cha discloses wherein when the control signal is in a first logic state [IS03 = active high], the plurality of first switches [SW1] and the plurality of second switches [SW2] are switched on to form the first electrical connection of the first reference signal [VREF1] and the second electrical connection [VREF2] of the second reference signal, and when the control signal is in a second logic state [off state], the plurality of first switches [SW1] and the plurality of second switches [SW2] are switched off to break the first electrical connection of the first reference signal [VREF1] and the second electrical connection of the second reference signal [VREF2].
Regarding claims 3, 11, and 18, Fig. 15 of Cha discloses Row Decoder [7500] generating control signal ISO. Since signal ISO is high and low, it is inherent that ISO is generated by inverting another signal.
Regarding claim 4, Fig. 2 of Cha discloses wherein the plurality of first switches and the plurality of second switches [150] are transistors of a same semiconductor type [paragraph 0029].
Regarding claim 5, 12, Fig. 6 and Fig. 7 of Cha discloses wherein the plurality of bit lines [BL1, BL2] include a first bit line and a second bit line [BLB1, BLB2], and the sense amplifier circuit [2300] comprises: a core sense circuit [2300], coupled to the first bit line, pre-charging the first bit line to a target voltage in a pre-charge phase [voltage on BL3, BLB3, during Precharge (T0 to T1) in Fig. 7], sensing values from the first bit line in a first sensing phase [between T2 and T3], and sensing values from the second bit line in a second sensing phase [LSB Sensing1, between T4 and T5]; and a bit line pre-charge branch circuit, coupled to the second bit line, pre-charging the second bit line to the target voltage in the pre-charge phase [during the period between T0 and T1], wherein the pre-charge phase [T0 to T1] is performed prior to the first sensing phase [between T2 and T3] and the second sensing phase [T5 and T6].
Regarding claims 6, 13, and 19 Fig. 6 of Cha discloses wherein the plurality of first switches and the plurality of second switches [2600] are switched off during the pre-charge phase.
Regarding claims 7, 14, and 20, Fig. 7 of Cha discloses wherein each of the first phase [between T2 and T3] and the second phase includes a first sub-phase [between T3 and T4] during which the enable signal is in the second logic state and a second sub-phase [between T4 and T5] during which the enable signal is in the first logic state, the plurality of first switches and the plurality of second switches [2600 in Fig. 6] of the reference sharing circuit are switched on during the first sub-phase, and the plurality of first switches and the plurality of second switches of the reference sharing circuit are switched off during the second sub-phase [switches 2600 are off during pre-charge].
Regarding claims 8, 15, Fig. 6 of Cha discloses wherein the first reference node [VREF1] supplies the first reference signal for sensing a first logic value from the plurality of bit lines [BL1, BLB1], and the second reference node [VREF2] supplies the second reference signal [VREF2] for sensing a second logic value from the plurality of bit lines.
Regarding claim 9, Fig. 4 of Cha discloses a memory device, comprising:
a memory array [300], including a plurality of memory cells [310, 320, 380, and 390];
a sense amplifier [BLSA], coupled to the memory array through a plurality of bit lines [BL1, BL2], sensing values stored in the plurality of memory cells [310, 320, 380, and 390] through the plurality of bit lines [BL1, BL2], wherein the sense amplifier comprises:
a sense amplifier circuit [BLSA], including a first reference node [N1] and a second reference node [N1, same is first node], sensing the plurality of bit lines [BL1, BL2] according to an enable signal; and
a reference sharing circuit [350], coupled to the sense amplifier circuit [BLSA], wherein the reference sharing circuit comprises:
a plurality of first switches [SW1], coupled to the first reference node [N1] of the sense amplifier circuit, controlling a first electrical connection of a first reference signal [VREF1] according to a control signal, wherein the control signal is derived from the enable signal; and
a plurality of second switches [SW2], coupled to the second reference node [N1] of the sense amplifier circuit, controlling a second electrical connection of a second reference signal [VREF2] according to the control signal [ISO3].
Regarding claim 16, Fig. 2 of Cha discloses an operation method of a sense amplifier [100] including a sense amplifier circuit [BLSA] and a reference sharing circuit [150], the reference sharing circuit is coupled to a first reference node [N1] and a second reference node [N1, same as first node] of the sense amplifier circuit, the operation method comprising:
receiving, by the sense amplifier circuit of the sense amplifier, an enable signal [IOS6, Fig. 6];
receiving, by the reference sharing circuit of the sense amplifier, a control signal [IS03], wherein the control signal is derived from the enable signal;
when the control signal is in a first logic state [when ISO3 is active high], switching on a plurality of first switches [SW1] and a plurality of second switches [Sw2] to form a first electrical connection of a first reference signal and a second electrical connection of a second reference signal [SW1 and SW2 are on], wherein the plurality of first switches and the plurality of second switches are included in the reference sharing circuit [within 150]; and
when the control signal is in a second logic state [when ISO3 is low], switching off the plurality of first switches and the plurality of second switches to break the first electrical connection of the first reference signal and the second electrical connection of the second reference signal [when SW1 and SW2 are off, the connection is also off].
Regarding claim 17, Fig. 7 of Cha discloses wherein the plurality of bit lines include a first bit line and a second bit line [BL3], and the method further comprising: pre-charging [between T0 and T1], by a core sense circuit of the sense amplifier circuit, the first bit line to a target voltage in a pre-charge phase [voltage on BL3 during T0 and T1]; pre-charging, by a bit line pre-charge branch circuit of the sense amplifier circuit, the second bit line [BLB3] to the target voltage in the pre-charge phase [voltage on BLB3 between T0 and T1]; sensing values from the first bit line in a first sensing phase [between T2 and T3], and sensing values from the second bit line in a second sensing phase [between T3 and T4], wherein the pre-charge phase [between T0 and T1] is performed prior to the first sensing phase [between T2 and T3] and the second sensing phase [between T3 and T4].
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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