DETAILED ACTION
The action is responsive to the following communications: the Application filed November 05, 2024 and the information disclosure statement (IDS) filed November 05, 2024 and January 22, 2025. This application is a CON of 18/325,170.
Claims 1-20 are pending. Claims 1, 7 and 13 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 05, 2024 and January 22, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Independent claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-20 of US Patent No. 12, 170,108. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,170,108
Comment
Claim 1. A control circuit comprising: a latch circuit configured to provide a first light sleep signal to a bit line reading switch
so that the bit line reading switch is cut off after a sense amplifier is enabled, wherein the latch circuit is configured to compare a sense amplifier enable signal and a clock signal.
Claim 1. A control circuit comprising:
a latch circuit configured to generate a first light sleep signal according to a sense amplifier enable signal and
to provide the first light sleep signal to a bit line reading switch so the bit line reading switch is cutoff after a
sense amplifier is enabled, wherein the latch circuit comprises a logic gate configured to compare the sense amplifier enable signal and a clock signal.
Note footnote1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US 2010/0214857).
Regarding independent claim 7 and its method independent claim 13 and claim 14, Hsu et al. disclose a read switch driving circuit comprising:
a latch circuit (see e.g., FIG. 7: 700 including latch circuit) configured to delay (FIG. 7: 717) an activation signal (FIG. 7: RSSL along with FIG. 4: RSSL) to a read switch (see FIG. 2A: 215a) such that a sense amplifier enable signal (FIG. 4: SAEN) precedes the activation signal (see e.g., FIG. 3: SAEN precedes RSSL), wherein the latch circuit is configured to compare (FIG. 4: 401) the sense amplifier enable signal (BA (110a) which is a input signal of SAEN) and a clock signal (FIG. 4: CLK_ACT).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 12, 15 and 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2010/0214857).
Regarding claims 8 and 15, Hsu et al. teach the limitations of claims 7 and 13, respectively.
Hus et al. do not explicitly disclose the latch circuit is configured to modify power to a memory device coupled thereto without interrupting read operations or write operations of the memory device.
However, modifying power to a memory device for read and write operations of the memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize modified power to a memory device because these conventional technology are well established in the art of the memory devices.
Regarding claims 12 and 19, Hsu et al. teach the limitations of claims 8 and 15.
Hus et al. further teach the memory device comprises a plurality of peripheral circuits including a local input/output circuit, a global input/output circuit, a local input/output controller, and a global input output controller (see e.g., FIGS. 1, 2A and 4, and accompanying disclosure; further it’s an inherent characteristic of memory devices).
Regarding claim 20, Hsu et al. teach the limitations of claim 19.
Hus et al. do not explicitly disclose operating the memory device in a power management mode including removing power from a portion of the peripheral circuits.
However, power management mode such as header and/or footer in a memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize modified power to a memory device because these conventional technology are well established in the art of the memory devices.
Allowable Subject Matter
Claims 1-6 are rejected but would be allowable if overcoming nonstatutory double patent rejection as indicated above rejection.
Claims 9-11 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if overcoming nonstatutory double patent rejection as indicated above rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 7 and 13, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights