DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
The term “have” after “said floating body region” in claim 1, line 3, claim 7, line 5 and claim 13, line 6 should be “having”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "said portions" in line 16. There is insufficient antecedent basis for this limitation in the claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 9,368,625 in view of Song (DE-102008033763-A1) or 최양규.(KR-100953646).
Regarding claim 1, claim 1 of the patent recites a semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;
a first region in electrical contact with said floating body region having a second conductivity type different from said first conductivity type;
a second region in electrical contact with said floating body region, spaced apart from said first region and having said second conductivity type;
a third region in electrical contact with said floating body region, spaced apart from said first and second regions and having said second conductivity type (claim 4);
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell; and
a gate positioned between said first and second regions;
Claims 1 and 4 of the patent do not recite said gate surrounds a portion of said floating body region and a doping concentration of said portions of said floating body region surrounded by said gate is different from a doping concentration of a part of said floating body region not surrounded by said gate. However, Song or 최양규 discloses the gate 22 surrounds a portion of floating body 18 for the gate insulating layer wo and the gate 22 to touch three sides (Song, Fig. 18 and The gate 22 surrounds the potentially floating body 18, For example, the gate insulating layer 20 and the gate 22 the entirety or a portion of two or more sides of the floating body 18 touch. As in 18 shown, touch the gate insulating layer 20 and the gate 22 a section of three sides of the floating body 18) or 최양규, Forming a gate oxide film on the exposed top surface of the floating body cell, forming a gate structure to surround the top of the floating body cell on which the gate oxide film is formed, and patterning the gate structure to expose both upper portions of the floating body cell). It would have been obvious to one having ordinary skill in the art to use the gate surrounding a portion of the floating body so that the insulating layer and the gate can touch three sides of the floating body and it would have been obvious to one having ordinary skill in the art to recognize that it would have been a matter of design choice to use a doping concentration of said portions of said floating body region surrounded by said gate different from a doping concentration of a part of said floating body region not surrounded by said gate since Applicant has not disclosed the use of different doping concentrations solves any stated problem and it appears that the memory cell would perform well with the doping concentrations of claims 1 and 4 of the patent.
Regarding claim 2, it would have been an obvious matter of design choice to arrange the third region between the substrate region and the floating body region.
Regarding claims 3 and 4, It is inherent that said state of the semiconductor memory cell is selected from at least first and second states (any memory cell can store at least two states) and said first and second states are stable states.
Regarding claim 5, it would have been obvious to one having ordinary skill in the art to recognize that the memory cel of claim 5 and the memory cell of claims 1 and 4 of the patent are identical in structure; therefore, the differences are only functional limitations.
Regarding claim 6, it would have been obvious to one having ordinary skill in the art to recognize that claim 6 of the patent recites the semiconductor memory cell of claim 1, wherein said floating body region and said first, second and third regions are provided in a fin structure.
Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,171,093 in view of Song (DE-102008033763-A1) or 최양규.(KR-100953646).
Regarding claim 1, claims 1 and 4 of the patent recites a semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type (claim 1, lines 7-11);
a first region in electrical contact with said floating body region having a second conductivity type different from said first conductivity type;
a second region in electrical contact with said floating body region, spaced apart from said first region and having said second conductivity type (claim 1, lines 14-30);
a third region in electrical contact with said floating body region, spaced apart from said first and second regions and having said second conductivity type (claim 4);
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell; and
a gate positioned between said first and second regions;
Claims 1 and 4 of the patent do not recite said gate surrounds a portion of said floating body region and a doping concentration of said portions of said floating body region surrounded by said gate is different from a doping concentration of a part of said floating body region not surrounded by said gate. However, Song or 최양규 discloses the gate 22 surrounds a portion of floating body 18 for the gate insulating layer wo and the gate 22 to touch three sides (Song, Fig. 18 and The gate 22 surrounds the potentially floating body 18, For example, the gate insulating layer 20 and the gate 22 the entirety or a portion of two or more sides of the floating body 18 touch. As in 18 shown, touch the gate insulating layer 20 and the gate 22 a section of three sides of the floating body 18) or 최양규, Forming a gate oxide film on the exposed top surface of the floating body cell, forming a gate structure to surround the top of the floating body cell on which the gate oxide film is formed, and patterning the gate structure to expose both upper portions of the floating body cell). It would have been obvious to one having ordinary skill in the art to use the gate surrounding a portion of the floating body so that the insulating layer and the gate can touch three sides of the floating body and it would have been obvious to one having ordinary skill in the art to recognize that it would have been a matter of design choice to use a doping concentration of said portions of said floating body region surrounded by said gate different from a doping concentration of a part of said floating body region not surrounded by said gate since Applicant has not disclosed the use of different doping concentrations solves any stated problem and it appears that the memory cell would perform well with the doping concentrations of claims 1 and 4 of the patent.
Regarding claim 2, it would have been an obvious matter of design choice to arrange the third region between the substrate region and the floating body region.
Regarding claims 3 and 4, It is inherent that said state of the semiconductor memory cell is selected from at least first and second states (any memory cell can store at least two states) and said first and second states are stable states.
Regarding claim 5, it would have been obvious to one having ordinary skill in the art to recognize that the memory cel of claim 5 and the memory cell of claims 1 and 4 of the patent are identical in structure; therefore, the differences are only functional limitations.
Regarding claim 6, it would have been obvious to one having ordinary skill in the art to recognize that claim 6 of the patent recites said floating body region and said first, second and third regions are provided in a fin structure.
Regarding claims 7 and 13, claims 7, 8 and 10 recite a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;
a first region in electrical contact with said floating body region having a second conductivity type different from said first conductivity type;
a second region in electrical contact with said floating body region, spaced apart from said first region and having said second conductivity type;
a third region in electrical contact with said floating body region, spaced apart from said first and second regions and having said second conductivity type;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell; and
wherein said third region is commonly connected to at least two of said semiconductor memory cells.
Claims 7, 8 and 10 of the patent do not recite said gate surrounds a portion of said floating body region and a doping concentration of said portions of said floating body region surrounded by said gate is different from a doping concentration of a part of said floating body region not surrounded by said gate. However, Song or 최양규 discloses the gate 22 surrounds a portion of floating body 18 for the gate insulating layer wo and the gate 22 to touch three sides (Song, Fig. 18 and The gate 22 surrounds the potentially floating body 18, For example, the gate insulating layer 20 and the gate 22 the entirety or a portion of two or more sides of the floating body 18 touch. As in 18 shown, touch the gate insulating layer 20 and the gate 22 a section of three sides of the floating body 18) or 최양규, Forming a gate oxide film on the exposed top surface of the floating body cell, forming a gate structure to surround the top of the floating body cell on which the gate oxide film is formed, and patterning the gate structure to expose both upper portions of the floating body cell). It would have been obvious to one having ordinary skill in the art to use the gate surrounding a portion of the floating body so that the insulating layer and the gate can touch three sides of the floating body and it would have been obvious to one having ordinary skill in the art to recognize that it would have been a matter of design choice to use a doping concentration of said portions of said floating body region surrounded by said gate different from a doping concentration of a part of said floating body region not surrounded by said gate since Applicant has not disclosed the use of different doping concentrations solves any stated problem and it appears that the memory cell would perform well with the doping concentrations of claims 7, 8 and 104 of the patent.
Regarding claims 8 and 14, it would have been an obvious matter of design choice to arrange the third region between the substrate region and the floating body region.
Regarding claims 9, 10, 15 and 16, It is inherent that said state of the semiconductor memory cell is selected from at least first and second states (any memory cell can store at least two states) and said first and second states are stable states.
Regarding claims 11 and 17, it would have been obvious to one having ordinary skill in the art to recognize that the memory cell, the memory array and the integrated circuit of claims 11 and 17 and the memory cell, the memory array and the integrated circuit of claims of the patent are identical in structure; therefore, the differences are only functional limitations.
Regarding claims 12 and 18, it would have been obvious to one having ordinary skill in the art to recognize that claim 12 of the patent recites said floating body region and said first, second and third regions are provided in a fin structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
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/HUAN HOANG/Primary Examiner, Art Unit 2827
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