Prosecution Insights
Last updated: July 17, 2026
Application No. 18/939,220

DUAL COLLIMATOR PHYSICAL VAPOR DEPOSITIONS PROCESSING CHAMBER

Final Rejection §103
Filed
Nov 06, 2024
Priority
Nov 07, 2023 — IN 202341075951
Examiner
MCDONALD, RODNEY GLENN
Art Unit
1794
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Applied Materials Inc.
OA Round
3 (Final)
63%
Grant Probability
Moderate
4-5
OA Rounds
1y 8m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 63% of resolved cases
63%
Career Allowance Rate
797 granted / 1260 resolved
-1.7% vs TC avg
Strong +24% interview lift
Without
With
+24.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
47 currently pending
Career history
1306
Total Applications
across all art units

Statute-Specific Performance

§103
76.5%
+36.5% vs TC avg
§102
3.1%
-36.9% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1260 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-3, 5, 7, 10, 25, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (CN 116864365 A) in view of Hanawa et al. (U.S. PGUB. U.S. 2005/0211546 A1) INDEPENDENT CLAIM 1: Regarding claim 1, Pan teaches a physical vapor deposition apparatus, comprising: a substrate support disposed within a processing region of a processing chamber of the physical vapor deposition apparatus, wherein the substrate support comprises a substrate supporting surface; a first flux optimizer disposed within the processing region, and comprising a plurality of apertures extending therethrough, the first flux optimizer being configured to be biased relative to a ground reference; a second flux optimizer disposed within the processing region, and comprising a plurality of apertures extending therethrough, the second flux optimizer being configured to be biased relative to the ground reference, wherein: the second flux optimizer is disposed between the first flux optimizer and the substrate support, and the first flux optimizer and the second flux optimizer are separated by a distance of about 0.01 cm to about 25 cm; a first power source coupled to the first flux optimizer or the second flux optimizer, the first power source configured to supply a voltage to either the first flux optimizer or the second flux optimizer, wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer. (Figs. 4, 5; Machine Translation – A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2. or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) The difference between Pan and claim 1 is that wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference is provided therebetween. Regarding wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference is provided therebetween (Claim 1), Hanawa et al. teach wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference is provided therebetween. (Paragraphs 0103, 0116, Fig. 19, Figs. 12A-E - [0103] FIGS. 12A through 12E illustrate one way of operating the multiple grids 108a-d so as to distribute the total potential difference between the plasma and the grid voltage among the multiple grids 108a-d. FIGS. 12A through 12E represent the time domain pulsed positive voltages of, respectively, the voltage sources 180', 180a, 180b, 180c, 180d. In FIG. 12A, ions are presented with ever-increasing attractive potentials (relative to the plasma potential of FIG. 12A) starting with the top grid 180a (with the greatest positive voltage) and progressing down to the bottom grid 180d (having the least positive voltage). The voltage sources may generate pulsed D.C. voltages or RF voltages or a combination of both. [0116] If only a single grid is present or if the multiple grids 108a-108d are used, they may be operated in the same manner as described above with reference to FIGS. 1-17. DEPENDENT CLAIM 2: Regarding claim 2, Pan teaches wherein the plurality of apertures in the first flux optimizer each comprise an opening that extends through the first flux optimizer, the plurality of apertures in the second flux optimizer each comprise an opening that extends through the first second flux optimizer, and the plurality of apertures in the first and second flux optimizers are aligned. (See Figs. 4, 5; Machine Translation) DEPENDENT CLAIM 3: Regarding claim 3, Pan teaches wherein a bias is applied to the first flux optimizer by supplying a voltage relative to ground to the first flux optimizer from the first power source. (See Figs. 4, 5; Machine Translation) DEPENDENT CLAIM 5: Regarding claim 5, Pan teaches wherein a bias is applied to the second flux optimizer by supplying a voltage to the second flux optimizer from the first power source. (See Fis. 4, 5; Machine Translation) DEPENDENT CLAIM 7: Regarding claim 7, Pan teaches wherein the first power source is coupled to the first flux optimizer, a second power source is coupled to the second flux optimizer, and a first bias is applied to the first flux optimizer by supplying a voltage to the first flux optimizer from the first power source and wherein a second bias is applied to the second flux optimizer by supplying a voltage to the second flux optimizer from the second power source. (See Figs. 4, 5; Machine Translation) INDEPENDENT CLAIM 10: Regarding claim 10, Pan teaches a physical vapor deposition apparatus, comprising: a top flux optimizer configured to be biased; an intermediate flux optimizer configured to be biased, wherein the top flux optimizer and the intermediate flux optimizer are separated by a first distance of about 0.01 cm to about 25 cm; a bottom flux optimizer configured to be biased, wherein the bottom flux optimizer and the intermediate flux optimizer are separated by a second distance of about 0.01 cm to about 25 cm; a top power source coupled to the top flux optimizer; an intermediate power source coupled to the intermediate flux optimizer; and a bottom power source coupled to the bottom flux optimizer. (See Figs. 4, 5; Machine Translation) The difference between Pan and claim 10 is that wherein a positive voltage difference is provided between at least one of the top flux optimizer and the intermediate flux optimizer, the intermediate flux optimizer and the bottom flux optimizer, or the top flux optimizer and the bottom flux optimizer is not discussed. Regarding claim 10, Hanawa et al. teach wherein a positive voltage difference is provided between at least one of the top flux optimizer and the intermediate flux optimizer, the intermediate flux optimizer and the bottom flux optimizer, or the top flux optimizer and the bottom flux optimizer. (Paragraphs 0103, 0116, Fig. 19, Figs. 12A-E) [0103] FIGS. 12A through 12E illustrate one way of operating the multiple grids 108a-d so as to distribute the total potential difference between the plasma and the grid voltage among the multiple grids 108a-d. FIGS. 12A through 12E represent the time domain pulsed positive voltages of, respectively, the voltage sources 180', 180a, 180b, 180c, 180d. In FIG. 12A, ions are presented with ever-increasing attractive potentials (relative to the plasma potential of FIG. 12A) starting with the top grid 180a (with the greatest positive voltage) and progressing down to the bottom grid 180d (having the least positive voltage). The voltage sources may generate pulsed D.C. voltages or RF voltages or a combination of both. [0116] If only a single grid is present or if the multiple grids 108a-108d are used, they may be operated in the same manner as described above with reference to FIGS. 1-17. DEPENDENT CLAIM 25: The difference not yet discussed is wherein the second flux optimizer comprises an entrance portion configured to decrease the rate at which the apertures are clogged by a sputtering material. Regarding claim 25, Pan teach in the Figures knife type edges for the collimators which are structurally the same as Applicant’s (Fig. 3D) and therefore teach apertures for preventing clogging. PNG media_image1.png 799 700 media_image1.png Greyscale DEPENDENT CLAIM 26: The difference not yet discussed is wherein the bottom flux optimizer comprises an entrance portion configured to decrease the rate at which the apertures are clogged by a sputtering material. Regarding claim 26, Pan teach in the Figures knife type edges for the collimators which are structurally the same as Applicant’s (Fig. 3D) and therefore teach apertures for preventing clogging. The motivation for utilizing the features of Hanawa et al. is that it allows for controlling the ion trajectory. (Paragraph 0116) Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified Pan by utilizing the features of Hanawa et al. because it allows for controlling ion trajectory. Claim(s) 1-5, 7, 10-17, 19, 25, 26, 27 are rejected under 35 U.S.C. 103 as being unpatentable over Hanawa et al. (U.S. PGUB. U.S. 2005/0211546 A1) in view of Pan (CN 116864365 A). INDEPENDENT CLAIM 1: Regarding claim 1, Hanawa et al. teach a physical vapor deposition apparatus (Paragraphs 0111-0122; Figs. 18-22) comprising: a substrate support (120) disposed within a processing region of a processing chamber of the physical vapor deposition apparatus, wherein the substrate support (120) comprises a substrate supporting surface; a first flux optimizer disposed within the processing region, and comprising a plurality of apertures extending therethrough, the first flux optimizer being configured to be biased relative to a ground reference (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053-0056, 0100, 0102); a second flux optimizer disposed within the processing region, and comprising a plurality of apertures extending therethrough, the second flux optimizer being configured to be biased relative to the ground reference, wherein the second flux optimizer is disposed between the first flux optimizer and the substrate support (Figs. 19, 22 - 180d; Paragraphs 0048, 0049, 0053-0056, 0100, 0102); a first power source coupled to the first flux optimizer (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053-0056, 0100, 0102) or the second flux optimizer, the first power source configured to supply a voltage to either the first flux optimizer or the second flux optimizer, wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053 - 0056, 0100, 0102) Hanawa et al. teach wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference is provided therebetween. (Paragraphs 0103, 0116, Fig. 19, Figs. 12A-E - [0103] FIGS. 12A through 12E illustrate one way of operating the multiple grids 108a-d so as to distribute the total potential difference between the plasma and the grid voltage among the multiple grids 108a-d. FIGS. 12A through 12E represent the time domain pulsed positive voltages of, respectively, the voltage sources 180', 180a, 180b, 180c, 180d. In FIG. 12A, ions are presented with ever-increasing attractive potentials (relative to the plasma potential of FIG. 12A) starting with the top grid 180a (with the greatest positive voltage) and progressing down to the bottom grid 180d (having the least positive voltage). The voltage sources may generate pulsed D.C. voltages or RF voltages or a combination of both. [0116] If only a single grid is present or if the multiple grids 108a-108d are used, they may be operated in the same manner as described above with reference to FIGS. 1-17. The difference between Hanawa et al. and claim 1 is that the first flux optimizer and the second flux optimizer are separated by a distance of about 0.01 cm to about 25 cm is not discussed. Regarding claim 1, Pan teaches the first flux optimizer and the second flux optimizer are separated by a distance of about 0.01 cm to about 25 cm. (Figs. 4, 5; Machine Translation – A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2, or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) DEPENDENT CLAIM 2: Regarding claim 2, Hanawa et al. teach wherein the plurality of apertures in the first flux optimizer each comprise an opening that extends through the first flux optimizer, the plurality of apertures in the second flux optimizer each comprise an opening that extends through the first flux optimizer, and the plurality of apertures in the first and second flux optimizers are aligned. (Paragraph 0048) DEPENDENT CLAIM 3: Regarding claim 3, Hanawa et al. teach wherein a bias is applied to the first flux optimizer by supplying a voltage relative to ground to the first flux optimizer from the first power source. (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053-0056, 0100, 0102) DEPENDENT CLAIM 4: Regarding claim 4, Hanawa et al. wherein the second flux optimizer (108d) is electrically grounded. (Paragraph 0105 - [0105] An alternative mode of operating the multiple grids 108a- 108d is to use the upper grids 108a-108c to accelerate ions from the ion generation sub-chamber 110 through the grid structure as described above, but use the bottom grid 108d as a neutralizer grid to at least partially (if not fully) neutralize the ion beam to create a beam of neutrals incident on the wafer 120. For this purpose, the bottom "neutralizer" grid 108d would have it orifices with exceptionally large aspect ratios and narrow diameters. Furthermore, a suitable neutralizing potential (e.g., ground) could be applied to the grid 108d.) DEPENDENT CLAIM 5: Regarding claim 5, Hanawa et al. teach wherein a bias is applied to the second flux optimizer by supplying a voltage to the second flux optimizer from the first power source. (Paragraph 0103 - [0103] FIGS. 12A through 12E illustrate one way of operating the multiple grids 108a-d so as to distribute the total potential difference between the plasma and the grid voltage among the multiple grids 108a-d. FIGS. 12A through 12E represent the time domain pulsed positive voltages of, respectively, the voltage sources 180', 180a, 180b, 180c, 180d. In FIG. 12A, ions are presented with ever-increasing attractive potentials (relative to the plasma potential of FIG. 12A) starting with the top grid 180a (with the greatest positive voltage) and progressing down to the bottom grid 180d (having the least positive voltage). The voltage sources may generate pulsed D.C. voltages or RF voltages or a combination of both.) DEPENDENT CLAIM 7: Regarding claim 7, wherein the first power source is coupled to the first flux optimizer, a second power source is coupled to the second flux optimizer, and a first bias is applied to the first flux optimizer by supplying a voltage to the first flux optimizer from the first power source and wherein a second bias is applied to the second flux optimizer by supplying a voltage to the second flux optimizer from the second power source. (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053-0056, 0100, 0102, 103) DEPENDENT CLAIM 10: Regarding claim 10, Hanawa et al. teach a physical vapor deposition apparatus, comprising: a top flux optimizer configured to be biased; an intermediate flux optimizer configured to be biased, wherein the top flux optimizer and the intermediate flux optimizer are separated by a first distance; a bottom flux optimizer configured to be biased, wherein the bottom flux optimizer and the intermediate flux optimizer are separated by a second distance; a top power source coupled to the top flux optimizer; an intermediate power source coupled to the intermediate flux optimizer; and a bottom power source coupled to the bottom flux optimizer. (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053-0056, 0100, 0101, 0102, 103) Hanawa et al. teach wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference is provided therebetween. (Paragraphs 0103, 0116, Fig. 19, Figs. 12A-E - [0103] FIGS. 12A through 12E illustrate one way of operating the multiple grids 108a-d so as to distribute the total potential difference between the plasma and the grid voltage among the multiple grids 108a-d. FIGS. 12A through 12E represent the time domain pulsed positive voltages of, respectively, the voltage sources 180', 180a, 180b, 180c, 180d. In FIG. 12A, ions are presented with ever-increasing attractive potentials (relative to the plasma potential of FIG. 12A) starting with the top grid 180a (with the greatest positive voltage) and progressing down to the bottom grid 180d (having the least positive voltage). The voltage sources may generate pulsed D.C. voltages or RF voltages or a combination of both. [0116] If only a single grid is present or if the multiple grids 108a-108d are used, they may be operated in the same manner as described above with reference to FIGS. 1-17. The difference between Hanawa et al. and claim 10 is that the distance between the various flux optimizers being 0.01 cm to about 25 cm is not discussed. Regarding claim 10, Pan teaches that the distance between the various flux optimizers being 0.01 cm to about 25 cm. (Figs. 4, 5; Machine Translation - A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2, or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) DEPENDENT CLAIM 11: The difference not yet discussed is wherein the intermediate flux optimizer comprises a plurality of biasable flux optimizers, that are separated from each other by a third distance that is about 0.01 cm and about 25 cm. Regarding claim 11, Pan teach the intermediate flux optimizer comprises a plurality of biasable flux optimizers, that are separated from each other by a third distance that is about 0.01 cm and about 25 cm. (Figs. 4, 5; Machine Translation - A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2, or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) DEPENDENT CLAIM 12: The difference not yet discussed is wherein a bias is applied to at least one of the plurality of biasable flux optimizers of the intermediate flux optimizers by supplying a voltage to the at least one of the plurality of biasable flux optimizer from the intermediate power source is not discussed. Regarding claim 12, Pan teaches wherein a bias is applied to at least one of the plurality of biasable flux optimizers of the intermediate flux optimizers by supplying a voltage to the at least one of the plurality of biasable flux optimizer from the intermediate power source. (Figs. 4, 5; Machine Translation – A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2, or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) DEPENDENT CLAIM 13: The difference not yet discussed is wherein the plurality of biasable flux optimizers are independently biasable. Regarding claim 13, Pan and Hanawa et al. show the flux optimizers to be independently biasable. (See Figures) DEPENDENT CLAIM 14: Regarding claim 14, Hanawa et al. teach wherein at least one of the top flux optimizer, the intermediate flux optimizer, and the bottom flux optimizer is electrically grounded. (Paragraph 0105 - [0105] An alternative mode of operating the multiple grids 108a-108d is to use the upper grids 108a-108c to accelerate ions from the ion generation sub-chamber 110 through the grid structure as described above, but use the bottom grid 108d as a neutralizer grid to at least partially (if not fully) neutralize the ion beam to create a beam of neutrals incident on the wafer 120. For this purpose, the bottom "neutralizer" grid 108d would have it orifices with exceptionally large aspect ratios and narrow diameters. Furthermore, a suitable neutralizing potential (e.g., ground) could be applied to the grid 108d.) DEPENDENT CLAIM 15: Regarding claim 15, Hanawa et al. teach wherein a voltage of about 10 V to about 200 V is supplied to the top flux optimizer from the top power source. (Paragraph 0104 - [0104] FIGS. 13A through 13E illustrates a mode of operating the multiple grids 108a-din which different grid voltages are employed to focus ion trajectories toward the center of each grid orifice 109 in selected ones of the multiple grids 108a-d, SO as to minimize or prevent ion collisions with grid surfaces. In the illustrated example, voltages of alternating polarities are applied to the succession of multiple grids 108a-d shown in FIG. 13A. FIGS. 13B through 13E illustrate the contemporaneous time domain voltage waveforms applied to the individual grids 108a through 108d respectively. The voltage waveforms depicted in FIGS. 13B through 13E are relative to the plasma potential and are peak values, and are provided as tutorial examples only. The top grid 108a is given a small positive (repulsive) voltage (e.g., 10 Volts)) DEPENDENT CLAIM 16: Regarding claim 16, wherein a voltage of about 10 V to about 200 V is supplied to the bottom flux optimizer from the bottom power source. (Paragraphs 0103 - [0103] FIGS. 12A through 12E illustrate one way of operating the multiple grids 108a-d so as to distribute the total potential difference between the plasma and the grid voltage among the multiple grids 108a-d. FIGS. 12A through 12E represent the time domain pulsed positive voltages of, respectively, the voltage sources 180', 180a, 180b, 180c, 180d. In FIG. 12A, ions are presented with ever- increasing attractive potentials (relative to the plasma potential of FIG. 12A) starting with the top grid 180a (with the greatest positive voltage) and progressing down to the bottom grid 180d (having the least positive voltage). The voltage sources may generate pulsed D.C. voltages or RF voltages or a combination of both.) INDEPENDENT CLAIM 17: Regarding claim 17, Hanawa et al. teach a method for depositing a film onto a substrate, the method comprising: applying a bias to at least one of a plurality of biasable flux optimizers disposed in a processing region of a processing chamber by supplying a voltage thereto, the voltage being supplied by a power source, wherein at least one of the plurality of biasable flux optimizers is grounded, and the plurality of biasable flux optimizers are positioned within the processing region between a sputtering target and a substrate support; and forming a film on a surface of a substrate disposed on the substrate support by sputtering a target material from the sputtering target by applying a bias to the target. (Figs. 19, 22 - 180a; Paragraphs 0048, 0049, 0053-0056, 0100, 0102, 0103, 0104, 0105) Hanawa et al. teach a positive voltage difference exists between a first biasable flux optimizer of the plurality of biasable flux optimizers and a second biasable flux optimizer of the plurality of biasable flux optimizers. (Paragraph 0104 - The top grid 108a is given a small positive (repulsive) voltage (e.g., 10 Volts), while the next grid 180b is given a large negative (attractive) voltage (e.g., -500 Volts). The third grid 108c is given a small positive (repulsive) voltage Paragraph 0105 - Furthermore, a suitable neutralizing potential (e.g., ground) could be applied to the grid 108d. “Ground” is still considered to be biasable because it is held at a defined electric potential and not floating but intentionally established. Therefore the third grid 108c is at a small positive potential and the bottom grid 108d is at a biasable ground potential. This would be a positive voltage difference between the two collimators in the plurality of collimators. The difference between Hanawa et al. and claim 17 is that the plurality of biasable flux optimizers are separated from other by a distance of about 0.01 cm to about 25 cm is not discussed. Regarding claim 17, Pan teaches the plurality of biasable flux optimizers are separated from other by a distance of about 0.01 cm to about 25 cm. (Figs. 4, 5; Machine Translation – A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2, or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) DEPENDENT CLAIM 19: Regarding claim 19, Hanawa et al. teach wherein the first flux optimizer (108d) is grounded and the second flux optimizer (108c) is biased. (Paragraphs 0104, 0105) DEPENDENT CLAIM 25: The difference not yet discussed is wherein the second flux optimizer comprises an entrance portion configured to decrease the rate at which the apertures are clogged by a sputtering material. Regarding claim 25, Pan teach in the Figures knife type edges for the collimators which are structurally the same as Applicant’s (Fig. 3D) and therefore teach apertures for preventing clogging. PNG media_image1.png 799 700 media_image1.png Greyscale DEPENDENT CLAIM 26: The difference not yet discussed is wherein the bottom flux optimizer comprises an entrance portion configured to decrease the rate at which the apertures are clogged by a sputtering material. Regarding claim 26, Pan teach in the Figures knife type edges for the collimators which are structurally the same as Applicant’s (Fig. 3D) and therefore teach apertures for preventing clogging. DEPENDENT CLAIM 27: The difference not yet discussed is wherein the second flux optimizer comprises an entrance portion configured to decrease the rate at which the apertures are clogged by a sputtering material. Regarding claim 27, Pan teach in the Figures knife type edges for the collimators which are structurally the same as Applicant’s (Fig. 3D) and therefore teach apertures for preventing clogging. The motivation for utilizing the features of Pan is that it allows for improving the filling capacity of openings by using ion control. (See Abstract) Therefore, it would have been obvious to one for ordinary skill in the art at the time the invention was made to have modified Hanawa et al. by utilizing the features of Pan because it allows for improving the filling capacity of openings by using ion control. 9. Claim(s) 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Hanawa et al. in view of Pan as applied to claims 1-5, 7, 10-17, 19, 25, 26, 27 above, and further in view of Tang et al. (U.S. Pat. 2015/0357171 A1). DEPENDENT CLAIMS 21, 23: The difference not yet discussed is wherein further comprising an electromagnet assembly disposed laterally around a portion of the processing chamber. Regarding claims 21, 23, Tang et al. teach an electromagnet assembly disposed laterally around a portion of a processing chamber. (Paragraph 0030) DEPENDENT CLAIMS 22, 24: The difference not yet discussed is wherein the electromagnet assembly comprises a magnetic coil assembly that encircles a perimeter of the processing chamber. Regarding claims 22, 24, Tang et al. teach wherein the electromagnet assembly comprises a magnetic coil assembly that encircles a perimeter of a processing chamber. (Paragraph 0030) The motivation for utilizing the features of Tang et al. is that it allows for increasing the plasma density. (Paragraph 0030) Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have utilized the features of Tang et al. because it allows for increasing the plasma density. Claim(s) 1, 5, 6, 8, 9, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Koizumi (JP 07-316806) in view of Pan (CN 116864365 A). INDEPENDENT CLAIM 1: Regarding claim 1, Koizumi teach a physical vapor deposition apparatus comprising: a substrate support disposed within a processing region of a processing chamber of the physical vapor deposition apparatus, wherein the substrate support comprises a substrate supporting surface; a first flux optimizer disposed within the processing region, and comprising a plurality of apertures extending therethrough, the first flux optimizer being configured to be biased relative to a ground reference; a second flux optimizer disposed within the processing region, and comprising a plurality of apertures extending therethrough, the second flux optimizer being configured to be biased relative to the ground reference, wherein the second flux optimizer is disposed between the first flux optimizer and the substrate support; a first power source coupled to the first flux optimizer or the second flux optimizer, the first power source configured to supply a voltage to either the first flux optimizer or the second flux optimizer, wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer. (See Abstract; Fig. 1) Koizumi teaches wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference (V) is provided therebetween. (See Abstract; Fig. 1) The difference between Koizumi and claim 1 is that the first flux optimizer and the second flux optimizer are separated by a distance of about 0.01 cm to about 25 cm. Regarding claim 1, Pan teaches the first flux optimizer and the second flux optimizer are separated by a distance of about 0.01 cm to about 25 cm. (Figs. 4, 5; Machine Translation - A further improvement is that the height between the first surface and the second surface of each collimator sheet unit is 0.5 cm to 15 cm. A further improvement is that the number of collimator sheet units is 1, 2, or 3 or more. A further improvement is that the spacing between each collimator sheet unit is 0.1 cm to 20 cm. A further improvement is that the bias voltage of each collimator chip unit is provided by an independent bias power supply, and the bias power supply provides DC bias voltage or AC bias voltage.) DEPENDENT CLAIM 5: The difference not yet discussed is wherein a bias is applied to the second flux optimizer by supplying a voltage to the second flux optimizer from the first power source. Regarding claim 5, Koizumi teaches wherein a bias is applied to the second flux optimizer by supplying a voltage to the second flux optimizer from the first power source. (See Abstract; Fig. 1) DEPENDENT CLAIM 6: Regarding claim 6, Koizumi teaches wherein the first flux optimizer is electrically grounded. (Fig. 1) DEPENDENT CLAIM 8: The difference not yet discussed is wherein a negative bias is supplied to the second flux optimizer relative to the first flux optimizer. Regarding claim 8, Pan teach freely selecting bias to the optimizers. (Machine Translation - The bias voltage of each collimator chip unit is based on the process requirements: the positive bias voltage of different sizes, the negative bias voltage of different sizes, the 0 bias voltage and the AC bias voltage of different waveforms and frequencies. Choose or switch between.) DEPENDENT CLAIM 9: Regarding claim 9, Koizumi teaches wherein a positive bias is supplied to the second flux optimizer relative to the first flux optimizer. (See Abstract) DEPENDENT CLAIM 25: The difference not yet discussed is wherein the second flux optimizer comprises an entrance portion configured to decrease the rate at which the apertures are clogged by a sputtering material. Regarding claim 25, Pan teach in the Figures knife type edges for the collimators which are structurally the same as Applicant’s (Fig. 3D) and therefore teach apertures for preventing clogging. PNG media_image1.png 799 700 media_image1.png Greyscale The motivation for utilizing the features of Pan is that it allows for improving the filling capacity of openings by using ion control. (See Abstract) Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified Koizumi by utilizing the features of Pan because it allows for improving the filling capacity of openings by using ion control. Response to Arguments Applicant's arguments filed March 5, 2026 have been fully considered but they are not persuasive. The 35 U.S.C. 102 rejection has been withdrawn based on Applicant’s amendment. In response to the argument that the prior art does not teach a physical vapor deposition apparatus, comprising a substrate support disposed within a processing region of a processing chamber of the physical vapor deposition apparatus a first flux optimizer disposed within the processing region the first flux optimizer being configured to be biased relative to a ground reference; a second flux optimizer disposed within the processing region the second flux optimizer being configured to be biased relative to the ground reference, wherein: the second flux optimizer is disposed between the first flux optimizer and the substrate support, and the first flux optimizer and the second flux optimizer are separated by a distance of about 0.01 cm to about 25 cm; a first power source coupled to the first flux optimizer or the second flux optimizer wherein the first power source is configured to generate a bias voltage between the first flux optimizer and the second flux optimizer such that a positive voltage difference (V) is provided therebetween, as recited in claim 1, it is argued that Pan teach the required separation distance between the collimators. Hanawa et al. and Koizumi teach the required potentials for the collimators to meet the positive voltage difference of the claims. In response to the argument that the prior art does not teach a physical vapor deposition apparatus, comprising a top flux optimizer configured to be biased, an intermediate flux optimizer configured to be biased a bottom flux optimizer configured to be biased a top power source coupled to the top flux optimizer; an intermediate power source coupled to the intermediate flux optimizer; and a bottom power source coupled to the bottom flux optimizer, wherein a positive voltage difference (V) is provided between at least one of the top flux optimizer and the intermediate flux optimizer, the intermediate flux optimizer and the bottom flux optimizer, or the top flux optimizer and the bottom flux optimizer, as recited in claim 10, it is argued that Pan teach the required separation distance between the collimators. Hanawa et al. and Koizumi teach the required potentials for the collimators to meet the positive voltage difference of the claims. In response to the argument that the prior art does not teach a method for depositing a film onto a substrate, the method comprising applying a bias to at least one of a plurality of biasable flux optimizers disposed in a processing region of a processing chamber by supplying a voltage thereto, wherein: at least one of the plurality of biasable flux optimizers is grounded, the plurality of biasable flux optimizers are positioned within the processing region between a sputtering target and a substrate support, wherein the plurality of biasable flux optimizers are separated from each other by a distance of about 0.01 cm to about 25 cm, and a positive voltage difference (V) exists between a first biasable flux optimizer of the plurality of biasable flux optimizers and a second biasable flux optimizer of the plurality of biasable flux optimizers, as recited in claim 17, it is argued that Pan teach the required separation distance between the collimators. Hanawa et al. and Koizumi teach the required potentials for the collimators to meet the positive voltage difference of the claims. It should be noted that the motivation for combining the references is for controlling the ion flux to the substrate. Furthermore with respect to Pan the collimators are independently biasable with selectable voltages. Because each collimator can be set to different potentials during normal operation, the system inherently and necessarily produces a positive voltage difference between at least one pair of collimators without any structural modification or additional mechanism. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RODNEY GLENN MCDONALD whose telephone number is (571)272-1340. The examiner can normally be reached Hoteling: M-Th every Fri off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Lin can be reached at 571-272-8902. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RODNEY G MCDONALD/Primary Examiner, Art Unit 1794 RM May 22, 2026
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Prosecution Timeline

Show 1 earlier event
Apr 07, 2025
Non-Final Rejection mailed — §103
Jun 11, 2025
Interview Requested
Jun 26, 2025
Applicant Interview (Telephonic)
Jun 27, 2025
Examiner Interview Summary
Aug 07, 2025
Response Filed
Nov 06, 2025
Non-Final Rejection mailed — §103
Mar 05, 2026
Response Filed
May 28, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Prosecution Projections

4-5
Expected OA Rounds
63%
Grant Probability
88%
With Interview (+24.3%)
3y 4m (~1y 8m remaining)
Median Time to Grant
High
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