Prosecution Insights
Last updated: August 16, 2026
Application No. 18/941,214

Component Carrier With Embedded Interposer Laterally Between Electrically Conductive Structures of Stack

Non-Final OA §102§112
Filed
Nov 08, 2024
Priority
Dec 20, 2019 — CN 201911326757.9 +1 more
Examiner
BURNS, TREMESHA WILLIS
Art Unit
Tech Center
Assignee
AT&S Austria Technologie & Systemtechnik AG
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
695 granted / 890 resolved
+18.1% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
49 currently pending
Career history
936
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.7%
-6.3% vs TC avg
§102
46.2%
+6.2% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 890 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the vertically extending electrically conductive through connection" on lines 18 – 19 (on lines 5 – 6, previous recitation in the plurality). There is insufficient antecedent basis for this limitation in the claim. Claim 19 recites the limitation "the vertically extending electrically conductive through connection" on lines 18 – 19 (on lines 5 – 6, previous recitation in the plurality). There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukasawa et al. (U.S. Patent Publication No. 2016/0293535). Regarding claim 1, in Figure 1A, Fukasawa discloses a component carrier, comprising: a stack (1) comprising a plurality of layers with an electrically conductive layer structure (12, 13, 31, 32) and an electrically insulating layer structure (11, 21, 22) arranged one on top of the other; and at least one interposer (100), having a plurality of vertically extending electrically conductive through connections (120, Figure 1B), for establishing an electrically conductive connection between a lower side and an upper side of the interposer, and being embedded in the electrically insulating layer structure of the stack (Figure 1A); wherein the at least one interposer is configured to provide a bridge function in a vertical and/or horizontal plane (Figure 1A); and wherein the component carrier further comprises at least one of the following features: electrically conductive structures (61, 62) in the stack laterally on both sides of the at least one interposer; the at least one interposer has at least one horizontally extending trace (41, 42, Figures 4A and 4B), configured for establishing an electrically conductive connection with at least a part of the vertically extending electrically conductive through connection (paragraph [0069]). Regarding claim 2, Fukasawa discloses wherein the at least one interposer is embedded in the stack (Figure 1A). Regarding claim 3, Fukasawa discloses wherein the at least one interposer is configured to bridge a component with respect to another component mounted on the component carrier (Figure 1A). Regarding claim 4, Fukasawa discloses wherein at least one horizontally extending trace is electrically decoupled from at least a part of the vertically extending electrically conductive through connection (Figure 1A). Regarding claim 5, Fukasawa discloses wherein the at least one interposer comprises glass (Figure 1A). Regarding claim 6, Fukasawa discloses protruding bumps, wherein the protruding bumps extend from the vertically extending electrically conductive through connection to at least one main surface of the stack and are flush with the at least one main surface of the stack (Figure 1A). Regarding claim 7, Fukasawa discloses wherein the protruding bumps are configured as copper pillars (Figure 1A). Regarding claim 8, Fukasawa discloses wherein the protruding bumps are included in the interposer as vertically extending conductive via connections for interconnection (Figure 1A). Regarding claim 9, Fukasawa discloses wherein a low current power supply through the component carrier directly passes to the interposer (Figure 1A). Regarding claim 10, Fukasawa discloses wherein the connection of the vertically extending electrically conductive through connection and the electrically conductive layer structure enables signal transmission directly from the component carrier to the interposer (Figure 1A). Regarding claim 11, Fukasawa discloses configured so that the interposer is free of a high current power supply; and/or wherein the high current power supply is through the component carrier directly to the at least one component and not through the interposer (Figure 1A). Regarding claim 12, Fukasawa discloses at least one stack-mounted component mounted on the stack, the stack-mounted component electrically connected with the interposer (Figure 1A). Regarding claim 13, Fukasawa discloses wherein a signal transmission from the interposer to the one or more stack-mounted component is via a direct pathway (Figure 1A). Regarding claim 14, Fukasawa discloses wherein a cavity is formed between one stack-mounted component and the stack, wherein another stack-mounted component mounted on the stack is accommodated in the cavity (Figure 1A). Regarding claim 15, Fukasawa discloses an encapsulation structure on the stack in which the at least one stack-mounted component is encapsulated, wherein the encapsulation structure is molded (Figure 1A). Regarding claim 16, Fukasawa discloses an encapsulation structure on the stack in which at least one stack-mounted component is encapsulated, and wherein the encapsulation structure is formed by lamination (Figure 1A). Regarding claim 17, Fukasawa discloses a first redistribution structure formed on one side of the stack and electrically connected with the interposer (Figure 1A). Regarding claim 18, Fukasawa discloses a second redistribution structure formed on an opposing other side of the stack and electrically connected with the interposer (Figure 1A). Regarding claim 19, in Figure 1A, Fukasawa discloses a method of manufacturing a component carrier, the method comprising: providing a stack (1) comprising a plurality of layers with an electrically conductive layer structure (12, 13, 31, 32) and an electrically insulating layer structure (11, 21, 22) arranged one on top of the other; embedding at least one interposer (100), having a plurality of vertically extending electrically conductive through connections (120, Figure 1B) for establishing an electrically conductive connection between a lower side and an upper side of the interposer, in the electrically insulating layer structure of the stack; wherein the at least one interposer is configured to provide a bridge function in a vertical and/or horizontal plane (Figure 1A); and wherein the component carrier further comprises at least one of the following features: electrically conductive structures (61, 62) in the stack laterally on both sides of the at least one interposer; the at least one interposer has at least one horizontally extending trace (41, 42, Figures 4A and 4B), configured for establishing an electrically conductive connection with at least a part of the vertically extending electrically conductive through connection (paragraph [0069]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Nov 08, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.3%)
2y 6m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 890 resolved cases by this examiner. Grant probability derived from career allowance rate.

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