DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed August 11, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 3 and 10 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, 7-10, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Non-Patent Literature J. H. Kim et al., "Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond," 2021 IEEE Hot Chips 33 Symposium (HCS), Palo Alto, CA, USA, 2021, pp. 1-26, doi: 10.1109/HCS52781.2021.9567191. (hereafter Kim) in view of EP 4278268 B1 to Jinshui Liu (hereafter Liu) and further in view of Non-Patent Literature Greenberg, Marc, “Using Multi-Channel Connections For Optimized LPDDR4 Power & Performance,” Semiconductor Engineering, April 14, 2016. (hereafter Greenberg).
Regarding Independent Claim 1, Kim discloses a dynamic random access memory (DRAM) device (DRAM device: Kim, Slide 6) comprising:
one or more stacks of memory dies (A stack of memory dies: Kim, Slide 13);
a configurable logic block on the base die (Programmable Computing Unit, PCU, integrated on base die: Kim, Slide 5)
to perform an operation on data (Integrated die including data processing unit: Kim, Slide 5) from
the one or more sub-ports or the one or more stacks of memory dies (HBM2 stack including multiple DRAM stacks: Kim, Slide 8).
The Kim presentation teaches stacking memory dies with a configurable base die for operation performance increases performance while being more energy efficient (Kim, Slide 6). The presentation relies on a single-port interface, however, and therefore does not teach the base die having at least two ports, wherein each of the at least two ports comprises one or more sub-ports, and wherein each sub-port has one or more channels operating in lockstep. Liu, on the other hand, teaches a dual-port memory module, wherein:
a base die having at least two ports (Describing a dual-port memory module: Liu, ¶[0023]),
wherein each of the at least two ports comprises one or more sub-ports (Ports consisting of a plurality of differential memory lanes, conceptually equivalent to a sub-port: Liu, ¶[0023]), and
wherein each sub-port has one or more channels (At least one channel is inherent in any interface).
Liu teaches a dual-port memory module is more flexible than other models, allowing more efficient use of computing resources and enabling composable memory for composable computing (Liu, ¶[0036]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible ports of Liu with the DRAM stack of Kim, with a reasonable expectation of success. Both inventions are well known in the field of stacked memory modules and the combination of known inventions with predictable results is obvious and not patentable.
Neither the Kim presentation nor Liu expressly disclose operating multiple channels in lockstep. Operating multiple channels in lockstep was previously known in the industry, however. See, for instance, Greenberg teaches the use of a Parallel, or lockstep, connection to allow all the DRAM devices to receive the same command and address but still transmit data over different byte lines (Greenberg, §Parallel (lockstep) connection). Greenberg further teaches this technique allows all the devices to remain in the same state and further describes the technique as familiar (Greenberg, §Parallel (lockstep) connection). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to operate multiple channels in lockstep, as was common in the art, in the stacked hierarchy of Kim, with a reasonable expectation of success. Application of a known technique to a piece of prior art ready for improvement is obvious and not patentable.
Regarding amended Claim 3, Liu discloses the DRAM device of claim 1, wherein
each of the one or more stacks of memory dies is accessible by each of the one or more sub-ports (Each port able to access part or all of the memory independently: Liu, ¶[0057]).
Regarding Claim 4, Liu discloses the DRAM device of claim 1, wherein
the configurable logic block is to perform a parallel computing operation (Teaching performing multiple operations in parallel: Liu, ¶[0041]).
Regarding Claim 7, Liu discloses the DRAM device of claim 1, further comprising
configurable routing circuitry on the base die to route data from the one or more sub-ports or the one or more stacks of memory dies (The host controller being able to route data one of two data ports, each consisting of a series of data lanes: Liu, ¶[0058]).
Regarding Claim 8 and the substantially similar limitations of Claim 17, Liu discloses the DRAM device of claim 1, wherein the at least two ports comprise:
a first port coupled to a first graphics processing unit (GPU) (Port coupled to a GPU: Liu, ¶[0051]); and
a second port coupled to a second GPU (Dual-ports being coupled to different hosts, which expressly includes GPUs, per Liu, ¶[0051]: Liu, ¶[0005]).
Regarding Claim 9, Liu discloses the DRAM device of claim 8, wherein:
the first port comprises a first sub-port and a second sub-port; and the second port comprises a third sub-port and a fourth sub-port (Each port disclosing 2, 4, 8, or more lanes: Liu, ¶[0058]).
Regarding amended Claim 10, Liu discloses the DRAM device of claim 8, wherein:
the first port comprises a first sub-port, a second sub-port, and a third sub-port; and the second port comprises a fourth sub-port, a fifth sub-port, and a sixth sub-port (Each port disclosing 2, 4, 8, or more lanes: Liu, ¶[0058]).
Claim(s) 2 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Non-Patent Literature J. H. Kim et al., "Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond," 2021 IEEE Hot Chips 33 Symposium (HCS), Palo Alto, CA, USA, 2021, pp. 1-26, doi: 10.1109/HCS52781.2021.9567191. (hereafter Kim), EP 4278268 B1 to Jinshui Liu (hereafter Liu), and Non-Patent Literature Greenberg, Marc, “Using Multi-Channel Connections For Optimized LPDDR4 Power & Performance,” Semiconductor Engineering, April 14, 2016. (hereafter Greenberg) in view of US 10,162,522 B1 to Xiaofei Li, et al. (hereafter Li).
Regarding Claim 2 and the substantially similar limitations of Claim 19, Kim discloses the DRAM device of claim 1, but fails to disclose the further limitations of Claim 2. Li, however, discloses a memory device, wherein
a number of the one or more sub-ports is configurable (Disclosing configurable pseudo-channels: Li, col.6:46-55).
Li teaches configurable pseudo-channels improves utilization of memory bandwidth because the address mapping improves synchronization of the channel traffics (Li, col.2:39-42). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible channels of Li with the stacked hierarchy of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory port management and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 5-6, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Non-Patent Literature J. H. Kim et al., "Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond," 2021 IEEE Hot Chips 33 Symposium (HCS), Palo Alto, CA, USA, 2021, pp. 1-26, doi: 10.1109/HCS52781.2021.9567191. (hereafter Kim), EP 4278268 B1 to Jinshui Liu (hereafter Liu), and Non-Patent Literature Greenberg, Marc, “Using Multi-Channel Connections For Optimized LPDDR4 Power & Performance,” Semiconductor Engineering, April 14, 2016. (hereafter Greenberg) in view of Non-Patent Literature Fang, Kevin et al. (NetDAM: Network Direct Attached Memory with Programmable In-Memory Computing ISA), October 28, 2021. (hereafter Fang).
Regarding Claim 5 and the substantially similar limitations of Claim 15, Kim discloses the DRAM device of claim 1, but fails to expressly disclose the further limitations of claim 5. Fang, however, discloses a memory system, wherein
the configurable logic block is to perform at least one of
a reduce operation,
an all-reduce operation,
a reduce-scatter operation (Disclosing a reduce-scatter operation: Fang, §3.1: Ring Reduce-Scatter),
a gather operation,
an all-gather operation (Disclosing a ring all-gather operation: Fang, §3.2: Ring All-Gather),
a scatter operation,
a broadcast operation,
a barrier operation,
a prefix sum operation,
an all-to-all operation,
a scatter-gather operation,
a collective communication operation,
a parallel prefix operation, or
a map-reduce operation.
Fang teaches the reduce-scatter and all-gather operations mitigates congestion by fully using the network bandwidth (Fang, §3: MPI ALLREDUCE). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to perform operations such as reduce-scatter and all-gather at the logic block level, with a reasonable expectation of success. Both inventions are well known in the field of GPU/ML communication and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 6 and the substantially similar limitations of Claim 20, Kim discloses the DRAM device of claim 1, but fails to expressly disclose the further limitations of claim 6. Fang, however, discloses a memory system, wherein
the configurable logic block is to perform at least
a portion of an all-reduce (Disclosing an all reduce operation: Fang, §3: MPI ALLREDUCE) operation
comprising a reduce-scatter operation (Disclosing a reduce-scatter operation: Fang, §3.1: Ring Reduce-Scatter) and an all-gather operation (Disclosing a ring all-gather operation: Fang, §3.2: Ring All-Gather).
Fang teaches the reduce-scatter and all-gather operations mitigates congestion by fully using the network bandwidth (Fang, §3: MPI ALLREDUCE). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to perform operations such as reduce-scatter and all-gather at the logic block level, with a reasonable expectation of success. Both inventions are well known in the field of GPU/ML communication and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 11-14, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Non-Patent Literature J. H. Kim et al., "Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond," 2021 IEEE Hot Chips 33 Symposium (HCS), Palo Alto, CA, USA, 2021, pp. 1-26, doi: 10.1109/HCS52781.2021.9567191. (hereafter Kim) in view of EP 4278268 B1 to Jinshui Liu (hereafter Liu).
Regarding Independent Claim 11, Kim discloses a memory device comprising:
a first memory stack (A stack of memory dies: Kim, Slide 13); and
a first base die (Programmable Computing Unit, PCU, integrated on base die: Kim, Slide 5),
wherein the first configurable logic circuitry is configured to perform an operation on data (Integrated die including data processing unit: Kim, Slide 5) from at least one of
the first port, the second port, or the first memory stack (HBM2 stack including multiple DRAM stacks: Kim, Slide 8).
The Kim presentation teaches stacking memory dies with a configurable base die for operation performance increases performance while being more energy efficient (Kim, Slide 6). The presentation relies on a single-port interface, however, and therefore fails to disclose the first base die comprising a first port, a second port, first configurable routing circuitry, and first configurable logic circuitry, wherein the first memory stack is accessible by the first port and the second port via the first configurable routing circuitry. Liu, on the other hand, teaches a dual-port memory module, wherein:
a first base die comprising
a first port, a second port (Describing a dual-port memory module: Liu, ¶[0023]),
first configurable routing circuitry (Disclosing configurable routing circuits: Liu, ¶[0061]), and
first configurable logic circuitry (Configurable logic circuits: Liu, ¶[0051]),
wherein the first memory stack is accessible by the first port and the second port via the first configurable routing circuitry (Each port able to access part or all of the memory independently: Liu, ¶[0057]).
Liu teaches a dual-port memory module is more flexible than other models, allowing more efficient use of computing resources and enabling composable memory for composable computing (Liu, ¶[0036]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible ports of Liu with the DRAM stack of Kim, with a reasonable expectation of success. Both inventions are well known in the field of stacked memory modules and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 12, Liu discloses the memory device of claim 11, wherein
the first port is programmably divided into a first sub-port and a second sub-port (Ports consisting of a plurality of differential memory lanes, conceptually equivalent to a sub-port: Liu, ¶[0023]),
wherein the first sub-port comprises the first configurable routing circuitry and the first configurable logic circuitry, wherein the second sub-port comprises second configurable routing circuitry and second configurable logic circuitry (The individual ports, each with separate pseudo-channels, including configurable routing and logic circuitry: Liu, ¶[0061]),
wherein the first configurable logic circuitry is configured to perform the operation on data from at least one of the first sub-port or the first memory stack, and wherein the second configurable logic circuitry is configured to perform the operation on data from at least one of the second sub-port or the first memory stack (All or part of each memory stack accessible by each mode or pseudo-channel, including data operations: Liu, ¶[0057]).
Regarding Claim 13, Kim discloses the memory device of claim 12, further comprising:
a second memory stack (Multiple stacks of memory dies: Kim, Slide 13); and
a second base die comprising:
a third sub-port with third configurable routing circuitry and third configurable logic circuitry (Ports consisting of a plurality of differential memory lanes, conceptually equivalent to a sub-port: Liu, ¶[0023]; The host controller being able to route data one of two data ports, each consisting of a series of data lanes: Liu, ¶[0058]); and
a fourth sub-port with fourth configurable routing circuitry and fourth configurable logic circuitry (Ports consisting of a plurality of differential memory lanes, conceptually equivalent to a sub-port: Liu, ¶[0023]; The host controller being able to route data one of two data ports, each consisting of a series of data lanes: Liu, ¶[0058]), wherein:
the first memory stack is accessible by the first sub-port, the second sub-port, the third sub-port, and the fourth sub-port (Each port able to access part or all of the memory independently: Liu, ¶[0057]);
the second memory stack is accessible by the first sub-port, the second sub-port, the third sub-port, and the fourth sub-port (Each port able to access part or all of the memory independently: Liu, ¶[0057]);
the third configurable logic circuitry is to perform the operation on data from at least one of the third sub-port or the second memory stack (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8); and
the fourth configurable logic circuitry is to perform the operation on data from at least one of the fourth sub-port or the second memory stack (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8).
Regarding Claim 14, Kim discloses the memory device of claim 12, further comprising:
a second memory stack (Multiple stacks of memory dies: Kim, Slide 13), wherein the first base die further comprises:
a third sub-port (Each port disclosing 2, 4, 8, or more lanes: Liu, ¶[0058]) with third configurable routing circuitry and third configurable logic circuitry (The individual ports, each with separate pseudo-channels, including configurable routing and logic circuitry: Liu, ¶[0061]); and
a fourth sub-port (Each port disclosing 2, 4, 8, or more lanes: Liu, ¶[0058]) with fourth configurable routing circuitry and fourth configurable logic circuitry (The individual ports, each with separate pseudo-channels, including configurable routing and logic circuitry: Liu, ¶[0061]), wherein:
the first memory stack is accessible by the first sub-port, the second sub-port, the third sub-port, and the fourth sub-port (Each port able to access part or all of the memory independently: Liu, ¶[0057]);
the second memory stack is accessible by the first sub-port, the second sub-port, the third sub-port, and the fourth sub-port (Each port able to access part or all of the memory independently: Liu, ¶[0057]);
the third configurable logic circuitry is to perform the operation on data from at least one of the third sub-port or the second memory stack (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8); and
the fourth configurable logic circuitry is to perform the operation on data from at least one of the fourth sub-port or the second memory stack (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8).
Regarding Independent Claim 16, Kim discloses a communication channel coupled between a first device and a second device, wherein the communication channel comprises:
a dynamic random access memory (DRAM) device (DRAM device: Kim, Slide 6) comprising:
a first base die (Programmable Computing Unit, PCU, integrated on base die: Kim, Slide 5) having
a first memory stack coupled to the first base die (Showing a first bank of memory coupled with the first base: Kim, Slide 9);
a first configurable logic block on the first base die (Programmable Computing Unit, PCU, integrated on base die: Kim, Slide 5);
a second base die having a second port coupled to the second device
wherein the second base die is coupled to the first base die (Showing the first and second base die connected: Kim, Slide 9);
a second memory stack coupled to the second base die (Showing a second bank of memory coupled with the second base: Kim, Slide 9); and
a second configurable logic block on the second base die (Programmable Computing Unit, PCU, integrated on base die: Kim, Slide 5), wherein:
the first configurable logic block is to perform a first operation on first data (Logic block will inherently perform an operation on associated data) from
the one or more sub-ports of the first port (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8),
the one or more sub-ports of the second port (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8); and
the second configurable logic block is to perform a second operation on second data from
the one or more sub-ports of the first port (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8),
the one or more sub-ports of the second port (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8).
The Kim presentation teaches stacking memory dies with a configurable base die for operation performance increases performance while being more energy efficient (Kim, Slide 6). The presentation relies on a single-port interface, however. Liu, on the other hand, teaches a communication channel coupled between a first device and a second device (Dual-ports being coupled to different hosts: Liu, ¶[0005]), wherein the communication channel comprises:
a dynamic random access memory (DRAM) device
having a first port (Describing a dual-port memory module: Liu, ¶[0023]) coupled to the first device,
wherein the first port comprises one or more sub-ports (Ports consisting of a plurality of differential memory lanes, conceptually equivalent to a sub-port: Liu, ¶[0023]);
a second base die having a second port coupled to the second device,
wherein the second port comprises one or more sub-ports (Ports consisting of a plurality of differential memory lanes, conceptually equivalent to a sub-port: Liu, ¶[0023]),
the first configurable logic block is to perform a first operation on first data (Logic block will inherently perform an operation on associated data) from
the first memory stack, or the second memory stack (Each port able to access part or all of the memory independently: Liu, ¶[0057]); and
the second configurable logic block is to perform a second operation on second data from
the first memory stack, or the second memory stack (Each port able to access part or all of the memory independently: Liu, ¶[0057]).
Liu teaches a dual-port memory module is more flexible than other models, allowing more efficient use of computing resources and enabling composable memory for composable computing (Liu, ¶[0036]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible ports of Liu with the DRAM stack of Kim, with a reasonable expectation of success. Both inventions are well known in the field of stacked memory modules and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Kim discloses the communication channel of claim 16, wherein
the first memory stack is accessible by the first device or the second device, and wherein the second memory stack is accessible by the first device or the second device (Logic circuitry configured to allow base die access to each connected data stack: Kim, Slide 8).
Response to Arguments
Applicant’s arguments filed August 11, 2026 have been fully considered but they are not persuasive.
With regards to independent Claim 1, Applicant’s first argument is the ‘Programmable Computing Unit’ of Kim is not ‘on’ the base die as claimed but rather, “Kim teaches HBM-PIM chips that include integrated PCUs and memory-core banks and the through-silicon via (TSV) and periphery region.” (Applicant’s Arguments/Remarks, p.9¶2). The relevant language in Claim 1 is, “a configurable logic block on the base die.” The claim does not claim the configurable logic block being ‘directly on,’ ‘formed in,’ or any other language that would indicate a direct physical connection between the configurable logic block and the base die. Standard semiconductor language does not require a direct bonding unless specified. A typical specification states that when an element is ‘on’ another element, it can be directly on that element or intervening elements may be present; ‘directly on’ is the phrase used when no intervening layers or elements are present. The applicant’s own specification describes stacks of memory dies on the base die, connected by vias, and treats those configurations as a single monolithic unit (“The first base die and the second base die may be stacked with through-silicon-vias(TSVs) and packaged together with the memory stack(s): 11/11/2024 Specification, ¶[0046]).
Consequently, prior art that places the configurable logic in an appropriate configuration relative to the base die teaches such a configuration, even if the PCU is not directly on the base die. Therefore, this argument is unpersuasive.
Applicant further argues the cited prior art fails to teach a ‘base die having at least two ports.’ (Applicant’s Arguments/Remarks, p.9¶1). This argument is based on two elements: that no port in Kim is identified as modifiable as taught in Liu and the dual ports of Liu are not necessarily located on the same base die as Kim’s PCU. (Applicant’s Arguments/Remarks, p.11¶2, continued on next page).
The first argument amounts to a piecemeal objection to the analysis. Liu is cited in this instance for the simple idea of a memory module comprising at least two configurable ports. It is not necessary to identify the specific port of Kim to be modified, merely that the two inventions in combination suffice to render the limitation obvious. As for the second argument, the claimed language ‘having’ is even less restrictive than the previously discussed ‘on.’ The broad language of Claim 1 does not require the ports of Liu be directly attached to the base die nor to the same die as the PCU, and therefore Broadest Reasonable Interpretation requires the claim be read as not requiring such a configuration. Therefore, this argument is also unpersuasive.
As for independent Claims 11 and 16, and all dependent claims, Applicant relies on identical grounds as those already addressed in regards to Claim 1 and therefore these arguments are found unpersuasive under identical reasoning. Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2026/0056909 A1 to Ronen Aharon Hyatt, et al.: Disclosing a flexible interface connection between separate hosts.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
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