DETAILED ACTION
This action is responsive to the Response to Election/Restriction filed November 14, 2024. Claims 1-9 and 21-31 are pending. Claims 10-20 have been cancelled. Claims 21-31 are new. Claims 1, 21 and 30 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on November 14, 2024, and March 6, 2026. These IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory Circuit with Sense Amplifier Having Isolated Transistors and Pre-Charged Internal Nodes.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: ND(1-6), Nd(1-6). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 9, 21, 27, 29 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo (US 20150036444).
Regarding claims 1, 21, and 30, Seo discloses a memory circuit comprising:
a memory cell (Fig. 2 where it illustrates memory cell MC);
a word line (as recited in claim 21: Fig. 2 where it illustrates word line WL).
a bit line (Fig. 4 where it illustrates bit line BL. Also recited as the 'a first bit line' in claim 30);
a bit line bar (Fig. 4 where it illustrates bit line bar BLB. Also recited as 'a second bit line' in claim 30);
a pass-gate transistor coupled to the word line (as recited in claim 21), memory cell and the bit line (Fig. 5 where it illustrates the transistor inside memory cell MC);
a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor (Fig. 5 where it illustrates sense amplifier 150. See also para. 51; "Sense amplifier 150 is connected to the bitlines connected to memory cell),
the sense amplifier comprising: a first path between the bit line and the bit line bar, the first path comprising:
a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node (Fig. 5 where it illustrates transistor ISO_1 receiving control signal ISO. See also para. 65; "a first isolation switch ISO_1", "ISO_1 operates according to isolation signal ISO");
and a first inverter (Fig. 5 where it illustrates the cross-coupled PMOS/NMOS sense amplifying unit of P_1/P_2/N_1/N_2) configured to receive a sense amplifier enable signal (Fig. 5 where it illustrates control signals LA and LAB), and being coupled between a second node and a third node (Fig. 5 where it illustrates the internal sensing nodes SABL and SABLB, or the intermediate connection points of the cross-coupled transistors. See also para. 67-69. It is noted that this is the classic cross-coupled inverter structure which is well understood in the art.);
and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal (para. 74; "Referring to FIGS. 7 and 8, in a step S110 of FIG. 7, sense amplifier 150 precharges bitline BL, complementary bitline BLB, sensing bitline SABL and complementary sensing bitline SABLB to a precharge voltage Vpre. Isolation signal ISO and offset cancellation signal OC are high, i.e., they have logic "high" states.". Regarding the control signals, see Fig. 8 and para. 75; "first and second isolation switches ISO_1 and ISO_2 and first and second offset cancellation switches OC_1 and OC_2 are turned on. Accordingly, bitline BL, complementary bitline BLB, sensing bitline SABL and complementary sensing bitline SABLB are connected to one node and each line is charged to precharge voltage Vpre.").
Regarding claims 7 and 27, Seo discloses the limitations of claims 1 and 21 respectively.
As applied, Seo further discloses further comprising:
an equalization circuit configured to equalize a voltage of the bit line and a voltage of the bit line bar in response to an equalization control signal (Fig. 18, transistor E_3 which is analogous to transistor T1 of the equalization circuit 204 of the instant application.),
the equalization circuit being coupled between the bit line and the bit line bar (Fig. 18 where it illustrates transistor E_3 coupled to bit line and bit line bar).
Regarding claims 9 and 29, Seo discloses the limitations of claims 1 and 21 respectively.
As applied, Seo further discloses wherein the memory cell comprises:
a capacitor coupled between the pass-gate transistor and a reference voltage supply (Fig. 2 where it illustrates memory cell MC).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6, 22-24, 26, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2015003644) in view of Yoon et al. ("A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage"; "Yoon").
Regarding claims 2 and 22, Seo discloses the limitations of claims 1 and 21 respectively.
As applied, Seo further discloses wherein the first path further comprises:
and a second isolation transistor configured to receive the isolation control signal, and being coupled between the third node and the bit line bar (Abstr. "a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal").
Seo discloses the isolation transistors and overall sense amplifier structure but is silent with respect to a capacitor coupled between the isolation-side node and the inverter input node.
However, Yoon teaches a first capacitor coupled between the first node and the second node (Fig. 4(a) where it illustrates capacitor Cc coupled to bit line BLT. See also Abstr. "an offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors);
Seo and Yoon are from the same field of endeavor as applicant' s invention directed to sense amplifiers within DRAM memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the coupling capacitor taught by Yoon into the path of Seo's sense for the predictable purpose of reducing the offset and improving the sensing margin – the same problem addressed by the instant application. Although Yoon places the coupling capacitor in a slightly different position within the amplifier path, a person of ordinary skill in the art would have recognized that as a routine design choice achieving the same functional benefit.
Regarding claims 3 and 23, Seo and Yoon combined disclose the limitations of claim 2 and 22 respectively.
As applied, Seo further discloses wherein the sense amplifier further comprises:
a second path between the bit line and the bit line bar (Fig. 4 where it illustrates the path from bit line BL, through transistor OC_1 and ISO_2 to bit line bar BLB),
the second path comprising:
a third isolation transistor configured to receive the isolation control signal, and being coupled between the bit line bar and a fourth node (Fig. 4 where it illustrates isolation transistor controlled by control signal ISO coupled to bit line bar BLB and the input to the sense amplifier 153);
and a second inverter (Fig. 5 where it illustrates the cross-coupled PMOS/NMOS sense amplifying unit of P_1/P_2/N_1/N_2) configured to receive the sense amplifier enable signal , (Fig. 5 where it illustrates control signals LA and LAB), and coupled between a fifth node and a sixth node (Fig. 5 where it illustrates the internal sensing nodes SABL and SABLB, or the intermediate connection points of the cross-coupled transistors. See also para. 67-69. It is noted that this is the classic cross-coupled inverter structure which is well understood in the art.);
wherein the pre-charge circuit is further coupled to the fourth node, and further configured to pre-charge the fourth node to the pre-charge voltage in response to the pre-charge control signal (para. 74; "Referring to FIGS. 7 and 8, in a step S110 of FIG. 7, sense amplifier 150 precharges bitline BL, complementary bitline BLB, sensing bitline SABL and complementary sensing bitline SABLB to a precharge voltage Vpre. Isolation signal ISO and offset cancellation signal OC are high, i.e., they have logic "high" states.". Regarding the control signals, see Fig. 8 and para. 75; "first and second isolation switches ISO_1 and ISO_2 and first and second offset cancellation switches OC_1 and OC_2 are turned on. Accordingly, bitline BL, complementary bitline BLB, sensing bitline SABL and complementary sensing bitline SABLB are connected to one node and each line is charged to precharge voltage Vpre.").
Regarding claims 4 and 24, Seo and Yoon disclose the limitations of claims 3 and 23 respectively.
As applied, Yoon further discloses wherein the second path further comprises:
a second capacitor coupled between the fourth node and the fifth node (Fig. 4(a) where it illustrates capacitor Cc coupled to bit line BLB. See also Abstr. "an offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors);
And as applied, Seo further discloses and a fourth isolation transistor configured to receive the isolation control signal, and being coupled between the sixth node and the bit line (Abstr. "a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal.).
Regarding claims 6 and 26, Seo and Yoon disclose the limitations of claims 4 and 24 respectively.
As applied, Seo further discloses wherein the pre-charge circuit comprises: a first transistor comprising:
a first terminal of the first transistor (Fig. 18, transistor E_1) being configured to receive the pre-charge control signal (Fig. 18, control signal PEQ);
a second terminal of the first transistor being coupled to the first node, the first isolation transistor (Fig. 18 where it illustrates transistor E_1 connected to transistor ISO_2);
and a third terminal of the first transistor being coupled to the pre-charge voltage (Fig. 18 where it shows transistor E_1 also connected to the precharge voltage Vpre);
and a second transistor comprising:
a first terminal of the second transistor (Fig. 18, transistor E_2) being configured to receive the pre- charge control signal (Fig. 18, control signal PEQ);
a second terminal of the second transistor being coupled to the fourth node, the third isolation transistor (Fig. 18 where it illustrates transistor E_2 connected to transistor ISO_1);
and a third terminal of the second transistor being coupled to the pre-charge voltage and the third terminal of the first P-type transistor (Fig. 18 where it shows transistor E_2 also connected to the precharge voltage Vpre).
While Fig. 18 of Seo discloses pre-charge transistors having terminal connections to the isolation transistor and controlled by a pre-charge signal, it does not explicitly contemplate those transistors as P-type and does not show the coupling capacitors.
Yoon teaches the use and connectivity of the coupling capacitors in the sense amplifier paths for offset cancellation. It would have been obvious to a person of ordinary skill in the art to (1) implement the pre-charge transistors of Seo as P-type MOSFETs and (2) include the coupling capacitors connected as taught by Yoon between relevant nodes.
Both modifications are nothing more than simple engineering design choices or implementation of known techniques that produce only predictable results.
Regarding claim 31, Seo discloses the limitations of claim 30.
As applied, Seo further discloses wherein the first path further comprises:
and a second isolation transistor configured to receive the isolation control signal, and being coupled between the third node and the second bit line (Abstr. "a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal");
and the sense amplifier further comprises:
a second path between the first bit line and the second bit line (Fig. 4 where it illustrates the path from bit line BL, through transistor OC_1 and ISO_2 to bit line bar BLB),
the second path comprising:
a third isolation transistor configured to receive the isolation control signal, and being coupled between the second bit line and a fourth node (Fig. 4 where it illustrates isolation transistor controlled by control signal ISO coupled to bit line bar BLB and the input to the sense amplifier 153);
and a second inverter (Fig. 5 where it illustrates the cross-coupled PMOS/NMOS sense amplifying unit of P_1/P_2/N_1/N_2) configured to receive the sense amplifier enable signal , (Fig. 5 where it illustrates control signals LA and LAB), and coupled between a fifth node and a sixth node (Fig. 5 where it illustrates the internal sensing nodes SABL and SABLB, or the intermediate connection points of the cross-coupled transistors. See also para. 67-69. It is noted that this is the classic cross-coupled inverter structure which is well understood in the art.)
wherein the pre-charge circuit is further coupled to the fourth node, and further configured to pre-charge the fourth node to the pre-charge voltage in response to the pre-charge control signal (para. 74; "Referring to FIGS. 7 and 8, in a step S110 of FIG. 7, sense amplifier 150 precharges bitline BL, complementary bitline BLB, sensing bitline SABL and complementary sensing bitline SABLB to a precharge voltage Vpre. Isolation signal ISO and offset cancellation signal OC are high, i.e., they have logic "high" states.". Regarding the control signals, see Fig. 8 and para. 75; "first and second isolation switches ISO_1 and ISO_2 and first and second offset cancellation switches OC_1 and OC_2 are turned on. Accordingly, bitline BL, complementary bitline BLB, sensing bitline SABL and complementary sensing bitline SABLB are connected to one node and each line is charged to precharge voltage Vpre.")
Seo discloses the isolation transistors and overall sense amplifier structure but is silent with respect to a capacitor coupled between the isolation-side node and the inverter input node.
However, Yoon teaches a first capacitor coupled between the first node and the second node (Fig. 4(a) where it illustrates capacitor Cc coupled to bit line BLT. See also Abstr. "an offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors);
Seo and Yoon are from the same field of endeavor as applicant' s invention directed to sense amplifiers within DRAM memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the coupling capacitor taught by Yoon into the path of Seo's sense for the predictable purpose of reducing the offset and improving the sensing margin – the same problem addressed by the instant application. Although Yoon places the coupling capacitor in a slightly different position within the amplifier path, a person of ordinary skill in the art would have recognized that as a routine design choice achieving the same functional benefit.
Claims 8 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2015003644)
Regarding claims 8 and 28, Seo discloses the limitations of claims 7 and 27 respectively.
As applied, Seo , wherein the equalization circuit comprises: a first transistor comprising:
a first terminal of the first transistor being configured to receive the equalization control signal (Fig. 18 where it illustrates transistor E_3 driven by equalization control signal PEQ);
a second terminal of the first transistor being coupled to the bit line (Fig. 18 where it depicts transistor E_3 coupled to the bit line);
and a third terminal of the first transistor being coupled to the bit line bar (Fig. 18 where it depicts transistor E_3 coupled to bit line bar).
Seo does not explicitly describe the equalizing transistor as a "P-type" transistor. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the equalizing switch of Seo as a P-type MOS transistor. Such an implementation is nothing more than the application of a known element (a P-type MOS transistor used as a switch) according to it's established function to yield a predictable result. A person of ordinary skill in the art would recognize that a P-type transistor is a conventional and suitable choice for the equalization switch in a DRAM sense amplifier circuit and the modification is no more than a routine engineering design choice.
Claims 5 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2015003644) in view of Yoon et al. ("A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage"; "Yoon") and further in view of Chi (US 20230071414).
Regarding claims 5 and 25, Seo and Yoon combined disclose the limitations of claims 4 and 24 respectively.
Seo as modified by Yoon provides the dual-path sense amplifier with isolation transistors and coupling capacitors, but is silent with respect to explicit placement of transistors parallel to the inverters of the sense amplifier.
However, Chi teaches wherein the sense amplifier further comprises:
a first transistor configured to receive a control signal, being coupled in parallel with the first inverter, and being between the second node and the third node (Fig. 1 where it illustrates transistor 11 in parallel with the first inverter of P1/N1);
and a second transistor configured to receive the control signal, being coupled in parallel with the second inverter, and being between the fifth node and the sixth node (Fig. 1 where it illustrates transistor 22 in parallel with the second inverter of P2/N2).
Seo, Yoon and Chi are from the same field of endeavor as applicant' s invention directed to sense amplifiers within DRAM memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chi's parallel transistors into the Seo/Yoon structure. Doing so would have yielded the predictable advantage of providing additional control of offset cancellation, equalization, or shorting during specific operating phases – functions that are well known and routinely implemented in DRAM sense amplifier design.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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