CTNF 18/947,810 CTNF 92342 DETAILED ACTION This action is responsive to the response filed 14 Nov 2024. Claims 1-20 are pending. Claims 1, 13, and 18 are independent. Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 9 – 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections – 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless — 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-15 AIA Claim s 1, 6, 7, 13, 14, 16, 18, and 19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Naidu, et al, U.S. Patent Application Publication 2017/0160317 (“ Naidu ”) . Regarding claim 1, Naidu teaches: A circuit, comprising: a first voltage provision circuit configured to provide a first output voltage at a first output node; and ( Naidu , fig 1, “[ 0033 ] The present description describes a high output voltage (V.oH) level and low output voltage (V.oL) level parametric test system that is configured to perform a V.oH parametric test and a V.oL parametric test”; a test circuit to test multiple pads of an I/O voltage driver circuit ). a test circuit coupled to the first voltage provision circuit and configured to test a driving current flowing through the first output node; ( Naidu , fig 2, “[ 0055 ] When the test controller 102 determines to perform the first, VoH test cycle, the test controller 102 may output the driver control signal IOdrv to the first I/O driver circuitry to cause the first I/O driver circuitry 202 to generate the first output voltage Voutl at the logic high level on the first output node PAD_l.”; the output from 1<j<N I/O driver is connected to the test circuit via MN1 current at the first output pad ). wherein the test circuit comprises a current mirror that comprises: a first transistor having a first source/drain terminal coupled to a test pin configured to receive a test current; and ( Naidu , fig 1, “[ 0042 ] The second NMOS transistor MN2 may be configured to receive a source current from a current source 108. The source current may generate the second bias voltage Vnbias as a fixed voltage. The gate terminal of the first NMOS transistor being connected to the node NBIAS may form a current mirror connection such that the current flowing through the first NMOS transistor MNl to sink current away from the jth output node PADj (FIG. 2) is a mirrored version of the source current supplied from the current source 108.”; MN1 (i.e. first transistor ) is connected to “current source 108” of figure 2, that the MN1 and MN2 combination forms a first half of a current mirror based on the output from the I/O drivers ). a second transistor having a first source/drain terminal coupled to the first output node. ( Naidu , fig 1, 2, 3, “[ 0042 ] transistor being connected to the node NBIAS, the diode connection of the second PMOS transistor MP2, and the gate terminal of the first PMOS transistor MPl being connected to the node PBIAS may form additional current mirror circuitries such that the current flowing through the second PMOS transistor MP2 and third NMOS transistor MN3 and the current flowing through the first PMOS transistor MPl to source current to the jth output node PADj (FIG. 2) may be mirrored versions of the source current supplied from the current source 108.”; MN3 and MP2 form the other side of the current mirror to test the I/O driver output ). Regarding claim 6, Naidu teaches The circuit of claim 1, wherein the first output voltage is configured for accessing a non-volatile memory device. ( Naidu , fig 5, 6, “[ 0089 ] FIG. 5 shows a flow chart of an example method of performing V 0 £lV oL parametric testing for a plurality of 1/O driver circuits of an electronic device. [ 0094 ] FIG. 6 shows a block diagram of an example non-volatile memory system 600 that may include the V oElV oL parametric system 100 of FIG. 1.”; that the testing circuit of fig 1 can be used as described in the method of of fig 5 on a NVM circuit as shown in fig 6 ). Regarding claim 7, Naidu teaches The circuit of claim 1, further comprising: a second voltage provision circuit configured to provide a second output voltage at a second output node; ( Naidu , fig 1, 2, 3, “[ 0001 ] In order to send and receive signals on the communications bus, the interface may include a plurality of input/output (I/O) driver circuits configured to drive lines of the communications bus, such as by pulling up and down the levels of output voltages to respective logic high and logic low output voltage levels. In[ 0054 ] In one example implementation, when the test controller 102 determines to perform the V oEIV oL parametric test for the first I/O driver circuit, as an example, the test controller 102 may output a first output switching control signal Vspadl to tum on a first output switch S_PAD_l and output the other output switching control signals Vspad2 to Vspadn to tum off the other output switches S_PAD 2 to S_PAD_N.”; a system that tests each I/O driver 1 - N for at least two voltage levels VoH and VoL; that the transistors can be driven to test for VoH ). Regarding claim 13, Naidu teaches: A circuit, comprising: a memory array; ( Naidu , fig 5, 6, “[ 0089 ] FIG. 5 shows a flow chart of an example method of performing V 0 £lV oL parametric testing for a plurality /O driver circuits of an electronic device. [ 0094 ] FIG. 6 shows a block diagram of an example non-volatile memory system 600 that may include the V oElV oL parametric system 100 of FIG. 1.”; that the testing circuit of fig 1 can be used as described in the method of of fig 5 on a NVM circuit as shown in fig 6 ). a voltage provision circuit configured to provide an output voltage at an output node, wherein the output voltage is configured for accessing the memory array; and ( Naidu , fig 1, “[ 0033 ] The present description describes a high output voltage (V.oH) level and low output voltage (V.oL) level parametric test system that is configured to perform a V.oH parametric test and a V.oL parametric test”; a test circuit to test multiple pads of an I/O voltage driver circuit ). a test circuit coupled to the voltage provision circuit and configured to test a driving current flowing through the output node to the memory array; ( Naidu , fig 2, “[ 0055 ] When the test controller 102 determines to perform the first, VoH test cycle, the test controller 102 may output the driver control signal IOdrv to the first I/O driver circuitry to cause the first I/O driver circuitry 202 to generate the first output voltage Voutl at the logic high level on the first output node PAD_l.”; the output from 1<j<N I/O driver is connected to the test circuit via MN1 current at the first output pad ). wherein the test circuit comprises a current mirror configured to mirror a test current as the driving current. ( Naidu , fig 1, “[ 0042 ] The second NMOS transistor MN2 may be configured to receive a source current from a current source 108. The source current may generate the second bias voltage Vnbias as a fixed voltage. The gate terminal of the first NMOS transistor being connected to the node NBIAS may form a current mirror connection such that the current flowing through the first NMOS transistor MNl to sink current away from the jth output node PADj (FIG. 2) is a mirrored version of the source current supplied from the current source 108.”; MN1 (i.e. first transistor ) is connected to “current source 108” of figure 2, that the MN1 and MN2 combination forms a first half of a current mirror based on the output from the I/O drivers ). Regarding claim 14, Naidu teaches: The circuit of claim 13, wherein the current mirror comprises: a first transistor having a first source/drain terminal coupled to a test pin configured to receive the test current; and ( Naidu , fig 1, “[ 0042 ] The second NMOS transistor MN2 may be configured to receive a source current from a current source 108. The source current may generate the second bias voltage Vnbias as a fixed voltage. The gate terminal of the first NMOS transistor being connected to the node NBIAS may form a current mirror connection such that the current flowing through the first NMOS transistor MNl to sink current away from the jth output node PADj (FIG. 2) is a mirrored version of the source current supplied from the current source 108.”; MN1 (i.e. first transistor ) is connected to “current source 108” of figure 2, that the MN1 and MN2 combination forms a first half of a current mirror based on the output from the I/O drivers ). a second transistor having a first source/drain terminal coupled to the output node through which the driving current flows. ( Naidu , fig 1, 2, 3, “[ 0042 ] transistor being connected to the node NBIAS, the diode connection of the second PMOS transistor MP2, and the gate terminal of the first PMOS transistor MPl being connected to the node PBIAS may form additional current mirror circuitries such that the current flowing through the second PMOS transistor MP2 and third NMOS transistor MN3 and the current flowing through the first PMOS transistor MPl to source current to the jth output node PADj (FIG. 2) may be mirrored versions of the source current supplied from the current source 108.”; MN3 and MP2 form the other side of the current mirror to test the I/O driver output ). Regarding claim 16, Naidu teaches: The circuit of claim 13, wherein the voltage provision circuit is one of a plurality of voltage provision circuits configured to provide a plurality of output voltages at respective output nodes for accessing the memory array, and ( Naidu , fig 1, 2, 3, “[ 0001 ] In order to send and receive signals on the communications bus, the interface may include a plurality of input/output (I/O) driver circuits configured to drive lines of the communications bus, such as by pulling up and down the levels of output voltages to respective logic high and logic low output voltage levels. In[ 0054 ] In one example implementation, when the test controller 102 determines to perform the V oEIV oL parametric test for the first I/O driver circuit, as an example, the test controller 102 may output a first output switching control signal Vspadl to tum on a first output switch S_PAD_l and output the other output switching control signals Vspad2 to Vspadn to tum off the other output switches S_PAD 2 to S_PAD_N.”; a system that tests each I/O driver 1 - N for at least two voltage levels VoH and VoL; that the transistors can be driven to test for VoH ). wherein the test circuit is coupled to the plurality of voltage provision circuits and configured to test a plurality of driving currents flowing through the respective output nodes to the memory array. ( Naidu , fig 1, 2, 3, “[ 0062 ] In addition, after the test controller 102 receives the third output signal from the comparator 110, the test controller may determine to perform the second, V oL test cycle for the first I/O driver circuit.”; that test circuit can be driven to test for second VoL levels as well as the first VoH levels ). Regarding claim 18, Naidu teaches: A method, comprising: receiving a test current and mirroring the test current as a driving current flowing through an output node of a voltage provision circuit, ( Naidu , fig 1, “[ 0033 ] The present description describes a high output voltage (V.oH) level and low output voltage (V.oL) level parametric test system that is configured to perform a V.oH parametric test and a V.oL parametric test”; a test circuit to test multiple pads of an I/O voltage driver circuit ). wherein the voltage provision circuit is configured to provide an output voltage at the output node; ( Naidu , fig 2, “[ 0055 ] When the test controller 102 determines to perform the first, VoH test cycle, the test controller 102 may output the driver control signal IOdrv to the first I/O driver circuitry to cause the first I/O driver circuitry 202 to generate the first output voltage Voutl at the logic high level on the first output node PAD_l.”; the output from 1<j<N I/O driver is connected to the test circuit via MN1 current at the first output pad ). increasing a level of the test current; and ( Naidu , fig 1, “[ 0042 ] The second NMOS transistor MN2 may be configured to receive a source current from a current source 108. The source current may generate the second bias voltage Vnbias as a fixed voltage. The gate terminal of the first NMOS transistor being connected to the node NBIAS may form a current mirror connection such that the current flowing through the first NMOS transistor MNl to sink current away from the jth output node PADj (FIG. 2) is a mirrored version of the source current supplied from the current source 108.”; MN1 (i.e. first transistor ) is connected to “current source 108” of figure 2, that the MN1 and MN2 combination forms a first half of a current mirror based on the output from the I/O drivers ). with the increasing level of the test current, identifying whether the output voltage drops to determine a level of the driving current. ( Naidu , fig 1, 2, 3, “[ 0042 ] transistor being connected to the node NBIAS, the diode connection of the second PMOS transistor MP2, and the gate terminal of the first PMOS transistor MPl being connected to the node PBIAS may form additional current mirror circuitries such that the current flowing through the second PMOS transistor MP2 and third NMOS transistor MN3 and the current flowing through the first PMOS transistor MPl to source current to the jth output node PADj (FIG. 2) may be mirrored versions of the source current supplied from the current source 108.”; MN3 and MP2 form the other side of the current mirror to test the I/O driver output ). Regarding claim 19, Naidu teaches The method of claim 18, wherein the voltage provision circuit comprises a low dropout voltage circuit. ( Naidu , fig 1, 2, “[ 0020 ] In another example embodiment, a parametric test method may be performed. The parametric test method may include: generating, with test circuitry and an input/output (I/O) driver circuit on an output node, a test voltage at a test level associated with one of a minimum high level or a maximum low level;”; the I/O drivers comprise a desired constant voltage circuit which operates above or below a threshold voltage exactly as described by applicant’s LDO drivers ) . Claim Rejections – 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-21-aia AIA Claim s 2 – 4, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Naidu in view of Naidu, ibid. (“ Naidu-2 ”) . Regarding claim 2, Naidu teaches the circuit of claim 1. Naidu teaches a fourth transistor having a first source/drain terminal and a second source/drain terminal connected to the first output node and the first source/drain terminal of the second transistor, respectively. ( Naidu , fig 1, 2, 3, “[ 0053 ] The comparator circuitry 104 may further include output switching circuitry that is configured to selectively or alternatingly couple the comparator 110 with the N-number of output nodes PAD_l to PAD_N. … The test controller 102 may be control the on and off states of the output switches S_PAD_l to S_PAD_Nby outputting output switching control switches Vspadl to Vspadn (denoted as Vspadl: Vspadn in FIG. 1) to the output switches S_PAD_l to S_PAD_N. …”; Switch circuits S1 and S2, for each of 1-N I/O outputs; associated with a high or low level (see fig 2); the two levels associated with at least Pull Up or Pull Down transistor ). Naidu does not explicitly teach wherein the current mirror comprises: a third transistor having a first source/drain terminal and a second source/drain terminal connected to the test pin and the first source/drain terminal of the first transistor, respectively; and . Naidu-2 teaches wherein the current mirror comprises: a third transistor having a first source/drain terminal and a second source/drain terminal connected to the test pin and the first source/drain terminal of the first transistor, respectively; and ( Naidu-2 , fig 1, 2, 3, “[ 0051 ] In one example configuration, to cause the reference voltage generation circuitry 112 to dynamically or alternatingly generate the reference voltage Vref at the three different high reference levels or the three different low reference levels, one of the three switches S3, S4, S5 may be turned on while the other two are turned off.”; Switch circuits S3, S4, and S5 each associated with a different reference voltage for testing each of the voltages from the different voltage drivers, the different reference voltages performing as a “test pin” or reference pin ). In view of the teachings of Naidu-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Naidu-2 to Naidu before the effective filing date of the claimed invention in order to teach switching elements. Accordingly, the prior art references disclose that it is known that Naidu ’s explicit switches S1 and S2 and electronic elements of the current mirror 106 are comprised of PMOS and NMOS transistors while switches S3, S4, and S5 of the same device are unspecified construction. It would have been “obvious to try” constructing S3, S4, and S5 from PMOS and NMOS using the known teachings of Naidu ’s S1 and S2 switches to modify Naidu ’s S3, S4, and S5 construction before the effective filing date of the claimed invention in order to improve similar devices in the same way where there are a finite number of identified, predictable solutions and there is no evidence of unexpected results. In this solution, using PMOS and NMOS switches is considered a finite, identified solution that would have produced predictable results. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Regarding claim 3, Naidu , as modified by Naidu-2 , teaches the circuit of claim 2. Naidu further teaches wherein the third transistor and the fourth transistor have their gate terminals configured to receive an enable signal indicating whether to test the driving current. ( Naidu , fig 1, 2, “[ 0040 ] Referring back to FIG. 1, the test controller 102 may be configured to output the first and second switching control signals Vsl, Vs2 to the first and second switches Sl, S2, respectively, [ 0052 ] The test controller 102 may be configured to output switching control signals Vs3, Vs4, Vs5 to the third, fourth, and fifth switches S3, S4, S5, respectively in order to turn on and off the third, fourth, and fifth switches S3, S4, S5 as desired.”; that each of the transistors of claim 2 can be controlled from controller 102 using enable switches ). Regarding claim 4, Naidu , as modified by Naidu-2 , teaches the circuit of claim 3. Naidu further teaches wherein the current mirror comprises: a fifth transistor having a gate terminal configured to receive a logically inverted version of the enable signal, a first source/drain terminal commonly connected to gate terminals of the first and second transistors, and a second source/drain terminal connected to ground. ( Naidu , fig 1, 2, “[ 0037 ] The first switch Sl may be configured to receive a first switching control signal Vsl to switch between an on state and an off state. Similarly, the second switch S2 may be configured to receive a second switching control signal Vs2 to switch between the on state and the off state. … The jth test circuitry may further include a first n-channel metal-oxide-semiconductor field-effect transistor (NMOS transistor) MNl having a source terminal connected to the low voltage VSS, a drain terminal connected to the second switch S2, and a gate terminal configured to receive a second bias voltage Vnbias. [ 0038 ] In addition, the first switching control signal Vsl may turn on the first switch Sl, and the second switching control signal Vs2 may turn off the second switch S2. [ 0036 ] The level of the low voltage VSS may be a ground reference voltage level,”; that the two switches, S1 and S2 can be operated singly by turning on S1 and turning S2 off, that the S2 can be considered part of the current mirror (see claim 1 where pad_j is input to current mirror source 108); that the source of S2 can be connected to VSS; that VSS can be a ground reference voltage level ). Regarding claim 15, Naidu teaches the circuit of claim 14. Naidu teaches: wherein to start mirroring the test current, the test circuit is configured to: receive an enable signal indicating whether to test the driving current via gate terminals of a third transistor and a fourth transistor, ( Naidu , fig 1, 2, “[ 0040 ] Referring back to FIG. 1, the test controller 102 may be configured to output the first and second switching control signals Vsl, Vs2 to the first and second switches Sl, S2, respectively, [ 0052 ] The test controller 102 may be configured to output switching control signals Vs3, Vs4, Vs5 to the third, fourth, and fifth switches S3, S4, S5, respectively in order to turn on and off the third, fourth, and fifth switches S3, S4, S5 as desired.”; that each of the transistors of claim 2 can be controlled from controller 102 using enable switches ). wherein the fourth transistor have a first source/drain terminal coupled to the output node and a second source/drain terminal connected to the first source/drain terminal of the second transistor. ( Naidu , fig 1, 2, 3, “[ 0053 ] The comparator circuitry 104 may further include output switching circuitry that is configured to selectively or alternatingly couple the comparator 110 with the N-number of output nodes PAD_l to PAD_N. … The test controller 102 may be control the on and off states of the output switches S_PAD_l to S_PAD_Nby outputting output switching control switches Vspadl to Vspadn (denoted as Vspadl: Vspadn in FIG. 1) to the output switches S_PAD_l to S_PAD_N. …”; Switch circuits S1 and S2, for each of 1-N I/O outputs; associated with a high or low level (see fig 2); the two levels associated with at least Pull Up or Pull Down transistor ). Naidu does not explicitly teach wherein the third transistor have a first source/drain terminal coupled to the test pin and a second source/drain terminal coupled to the first transistor, and . Naidu-2 teaches wherein the third transistor have a first source/drain terminal coupled to the test pin and a second source/drain terminal coupled to the first transistor, and ( Naidu-2 , fig 1, 2, 3, “[ 0051 ] In one example configuration, to cause the reference voltage generation circuitry 112 to dynamically or alternatingly generate the reference voltage Vref at the three different high reference levels or the three different low reference levels, one of the three switches S3, S4, S5 may be turned on while the other two are turned off.”; Switch circuits S3, S4, and S5 each associated with a different reference voltage for testing each of the voltages from the different voltage drivers, the different reference voltages performing as a “test pin” or reference pin ). In view of the teachings of Naidu-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Naidu-2 to Naidu before the effective filing date of the claimed invention in order to teach switching elements. Accordingly, the prior art references disclose that it is known that Naidu ’s explicit switches S1 and S2 and electronic elements of the current mirror 106 are comprised of PMOS and NMOS transistors while switches S3, S4, and S5 of the same device are unspecified construction. It would have been “obvious to try” constructing S3, S4, and S5 from PMOS and NMOS using the known teachings of Naidu ’s S1 and S2 switches to modify Naidu ’s S3, S4, and S5 construction before the effective filing date of the claimed invention in order to improve similar devices in the same way where there are a finite number of identified, predictable solutions and there is no evidence of unexpected results. In this solution, using PMOS and NMOS switches is considered a finite, identified solution that would have produced predictable results. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Regarding claim 20, Naidu teaches the method of claim 18. Naidu teaches: wherein the test current is received and mirrored by a test circuit, comprising: a first transistor having a first source/drain terminal coupled to a test pin configured to receive the test current; and ( Naidu , fig 1, “[ 0042 ] The second NMOS transistor MN2 may be configured to receive a source current from a current source 108. The source current may generate the second bias voltage Vnbias as a fixed voltage. The gate terminal of the first NMOS transistor being connected to the node NBIAS may form a current mirror connection such that the current flowing through the first NMOS transistor MNl to sink current away from the jth output node PADj (FIG. 2) is a mirrored version of the source current supplied from the current source 108.”; MN1 (i.e. first transistor ) is connected to “current source 108” of figure 2, that the MN1 and MN2 combination forms a first half of a current mirror based on the output from the I/O drivers ). a second transistor having a first source/drain terminal coupled to the output node and configured to mirror the test current through the output node, ( Naidu , fig 1, 2, 3, “[ 0042 ] transistor being connected to the node NBIAS, the diode connection of the second PMOS transistor MP2, and the gate terminal of the first PMOS transistor MPl being connected to the node PBIAS may form additional current mirror circuitries such that the current flowing through the second PMOS transistor MP2 and third NMOS transistor MN3 and the current flowing through the first PMOS transistor MPl to source current to the jth output node PADj (FIG. 2) may be mirrored versions of the source current supplied from the current source 108.”; MN3 and MP2 form the other side of the current mirror to test the I/O driver output ). wherein to mirror the test current, the method comprises: receiving an enable signal indicating whether to test the driving current via gate terminals of a third transistor and a fourth transistor, ( Naidu , fig 1, 2, “[ 0040 ] Referring back to FIG. 1, the test controller 102 may be configured to output the first and second switching control signals Vsl, Vs2 to the first and second switches Sl, S2, respectively, [ 0052 ] The test controller 102 may be configured to output switching control signals Vs3, Vs4, Vs5 to the third, fourth, and fifth switches S3, S4, S5, respectively in order to turn on and off the third, fourth, and fifth switches S3, S4, S5 as desired.”; that each of the transistors of claim 2 can be controlled from controller 102 using enable switches ). the fourth transistor having a first source/drain terminal and a second source/drain terminal connected to the output node and the first source/drain terminal of the second transistor, respectively. ( Naidu , fig 1, 2, 3, “[ 0053 ] The comparator circuitry 104 may further include output switching circuitry that is configured to selectively or alternatingly couple the comparator 110 with the N-number of output nodes PAD_l to PAD_N. … The test controller 102 may be control the on and off states of the output switches S_PAD_l to S_PAD_Nby outputting output switching control switches Vspadl to Vspadn (denoted as Vspadl: Vspadn in FIG. 1) to the output switches S_PAD_l to S_PAD_N. …”; Switch circuits S1 and S2, for each of 1-N I/O outputs; associated with a high or low level (see fig 2); the two levels associated with at least Pull Up or Pull Down transistor ). Naidu does not explicitly teach the third transistor having a first source/drain terminal and a second source/drain terminal connected to the test pin and the first source/drain terminal of the first transistor, respectively, and . Naidu-2 teaches the third transistor having a first source/drain terminal and a second source/drain terminal connected to the test pin and the first source/drain terminal of the first transistor, respectively, and ( Naidu-2 , fig 1, 2, 3, “[ 0051 ] In one example configuration, to cause the reference voltage generation circuitry 112 to dynamically or alternatingly generate the reference voltage Vref at the three different high reference levels or the three different low reference levels, one of the three switches S3, S4, S5 may be turned on while the other two are turned off.”; Switch circuits S3, S4, and S5 each associated with a different reference voltage for testing each of the voltages from the different voltage drivers, the different reference voltages performing as a “test pin” or reference pin ). In view of the teachings of Naidu-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Naidu-2 to Naidu before the effective filing date of the claimed invention in order to teach switching elements. Accordingly, the prior art references disclose that it is known that Naidu ’s explicit switches S1 and S2 and electronic elements of the current mirror 106 are comprised of PMOS and NMOS transistors while switches S3, S4, and S5 of the same device are unspecified construction. It would have been “obvious to try” constructing S3, S4, and S5 from PMOS and NMOS using the known teachings of Naidu ’s S1 and S2 switches to modify Naidu ’s S3, S4, and S5 construction before the effective filing date of the claimed invention in order to improve similar devices in the same way where there are a finite number of identified, predictable solutions and there is no evidence of unexpected results. In this solution, using PMOS and NMOS switches is considered a finite, identified solution that would have produced predictable results. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)) . 07-21-aia AIA Claim s 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Naidu in view of Kim, et al, U.S. Patent Application Publication 2011/0096587 (“ Kim ”) . Regarding claim 5, Naidu teaches the circuit of claim 1. Naidu teaches wherein the first transistor has a first size and the second transistor has a second size, and ( Naidu , fig 1, 2, “[ 0043 ] The current mirror circuitry may provide a relatively high output resistance such that it helps keep the current sourced to and sunk from the output nodes PAD_l to PAD_N constant regardless of load. Also, the width-to length (W/L) ratios of the first NMOS transistor MNl may be a multiple (M) times the W /L ratio of the second NMOS transistor MNl so that the first NMOS transistors MNl draw desired amounts of current away from the output nodes PAD_l to PAD_N.”; that the transistors in a current mirror can have relatively larger or smaller sizes depending on testing results desired ). Naidu does not explicitly teach wherein the second size is larger than the first size. . Kim teaches wherein the second size is larger than the first size. ( Kim , fig 1, 2A, 2C, “[ 0030 ] In another aspect of the present disclosure, the programmable current mirror circuits are comprised of field effect transistors (FETs), the aspect ratios of which--that is, the ratio of the width of the gate to the length of the gate within the structure of the FET--are selected to provide desired scale factors through the programmable current mirror circuits. [ 0056 ] FIG. 2C provides a table of configuration settings (that is, scale factor selections responsive to the first and second banks of control signals 150 and 160, respectively) which can be used to apply various sense currents (I.sub.3) to the memory cell under test 140.”; that the widths of transistors can be scaled larger or smaller to generate a desired ratio of current in a :current mirror” to test different aspects of a memory cell ). In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Naidu before the effective filing date of the claimed invention in order to teach testing circuits. The teachings of Kim , in the same or in a similar field of endeavor with Naidu , can combine Naidu ’s differently scaled widths of transistors with Kim ’s more explicit scaling of current mirror transistors The slightly different sizing of transistors in a testing circuit merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Regarding claim 8, Naidu teaches the circuit of claim 7. Naidu teaches wherein the current mirror comprises: a third transistor having a first source/drain terminal coupled to the second output node; ( Naidu , fig 1, 2, 3, “[ 0040 ] Referring to fig 1, … the bias circuitry 106 may be configured to generate the first bias voltage Vpbias and output the first bias voltage Vpbias to the gate terminals of the first PMOS transistors MPl of each of the N-number of test circuits.”; that the current mirror of circuit 106 has two outputs NBIAS and PBIAS which are directed towards the transistors selected in figure 2 ). Naidu does not explicitly teach wherein the first transistor has a first size, the second transistor has a second size, and the third transistor has a third size, the second and third sizes being different from each other and each larger than the first size. . Kim teaches wherein the first transistor has a first size, the second transistor has a second size, and the third transistor has a third size, the second and third sizes being different from each other and each larger than the first size. ( Kim , fig 1, 2A, 2C, “[ 0030 ] In another aspect of the present disclosure, the programmable current mirror circuits are comprised of field effect transistors (FETs), the aspect ratios of which--that is, the ratio of the width of the gate to the length of the gate within the structure of the FET--are selected to provide desired scale factors through the programmable current mirror circuits. [ 0056 ] FIG. 2C provides a table of configuration settings (that is, scale factor selections responsive to the first and second banks of control signals 150 and 160, respectively) which can be used to apply various sense currents (I.sub.3) to the memory cell under test 140.”; that the widths of transistors in a current mirror can be scaled larger or smaller to generate a desired ratio of current in a :current mirror” to test different aspects of a memory cell ). In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Naidu before the effective filing date of the claimed invention in order to teach testing circuits. The teachings of Kim , in the same or in a similar field of endeavor with Naidu , can combine Naidu ’s differently scaled widths of transistors with Kim ’s more explicit scaling of current mirror transistors The slightly different sizing of transistors in a testing circuit merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Donald HB Braswell/ Primary Examiner, Art Unit 2825 Application/Control Number: 18/947,810 Page 2 Art Unit: 2825 Application/Control Number: 18/947,810 Page 3 Art Unit: 2825
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