DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
An Information Disclosure Statement has not been entered. Applicant is reminded of the duty to disclose material information under 37 CFR 1.56. If applicant wishes to have an Information Disclosure Statement made of record, please submit form PTO/SB/08, along with any statements and fees required by 37 CFR 1.97, prior to or along with the payment of the issue fee.
Priority
The present application, 18/948,565, is a continuation of Application 18/472,282, filed on 9/22/2023, which is a continuation of Application 17/733,785, filed on 04/29/2022, which is a divisional of 16/216,073, filed on 12/11/2018, which claims priority to Provisional Application 62/734,084, filed on 9/20/2018. The claim for priority through this chain is acknowledged as properly supported under 35 U.S.C. § 120 for the non-provisional applications and 35 U.S.C. § 119(e) for the provisional application.
Election/Restrictions
Applicant’s election without traverse of Claims 9-20 in the reply filed on August 31, 2026 is acknowledged. At applicant’s request, Claims 1-8 have been cancelled.
Response to Amendment
The amendment filed August 31, 2062 has been entered. Claims 9-28 remain pending in this application. Claims 1-8 drawn to non-elected invention have been cancelled at applicant’s request. Claims 12-14 and 17 have been amended, adding no new matter. Claims 21-28 have been added, adding no new matter.
Claim Objections
Claim 21 objected to because of the following informalities:
New Claim 21: “through via structures penetrating though the circuit layers.” Will be read as “through the circuit layers.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 28 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 28 recites the limitation “the first bit line” and “the second bit line.” There is insufficient antecedent basis for this limitation in the claim. Claim depends from New Claim 21, which merely recites “a respective bit line.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9-16 and 21-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0130068 A1 to Chih-Yu Lin, et al. (hereafter Li) in view of US 8,411,494 B2 to Alexander Mikhailovich Shukh (hereafter Shukh) and further in view of US 2017/0179153 A1 to Hiroyuki Ogawa, et al. (hereafter Ogawa).
Regarding Independent Claim 9, Lin discloses a memory device, comprising:
a plurality of circuit layers disposed one above another (Lin, ¶[0021]),
each circuit layer comprising one or more memory cell arrays (Lin, ¶[0021]);
a plurality of first conductive through via structures penetrating though the circuit layers (Lin, ¶[0021]); and
a plurality of bit lines (Lin, ¶[0022]),
each bit line comprising a plurality of bit line segments disposed on the circuit layers respectively (Lin, ¶[0022]),
the bit line segments being electrically connected through one of the first conductive through via structures (Lin, ¶[0022]),
each bit line segment being coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bit line segment is disposed (Lin, ¶[0022]);
a plurality of second conductive through via structures penetrating through the circuit layers (Lin, ¶[0016]).
Lin discloses a three-dimensional memory circuit comprising multiple bonded layers interconnected by vias. Lin does expressly disclose the memory device comprising a word line driver circuit on a first layer, connected to and driving word lines on other layers through the vias. Shukh, however, discloses a layered memory array circuit including:
wherein the circuit layers comprise a first circuit layer and a second circuit layer (Shukh, col.6:53-54), and
the first circuit layer comprises a first word line driver circuit (Shukh, col.6:62-63 and Shukh, Figure 6);
the memory device further comprises
a plurality of word lines disposed on the second circuit layer (Word lines 19-1-1 and 19-1-2: Shukh, Figure 5), and
the second conductive through via structures are electrically connected between the first word line driver circuit of the first circuit layer and the word lines disposed on the second circuit layer (Shukh, col.6:60-62)
Once Lin has taught layering memory arrays connected by bias to connect bit line segments, and Shukh has taught layering word lines and word line circuitry in a similar manner, routing word line addresses and drive onto parallel is an obvious implementation choice. Doing so would allow repeating the word line driver on each layer, saving circuit space and cost. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to mimic the bit line driver and vias of Lin to implement the word line driver and vias of Shukh, with a reasonable expectation of success. Both inventions are well known in the field of stacked memory array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Lin and Shukh teach the underlying architecture wherein memory arrays are formed on different layers, with word line driver circuitry located on the first layer. Ogawa makes explicit the connecting configuration, that is the first word line driver on the first layer driving the word line on the other layer through vias (Ogawa, ¶[0251]). Ogawa teaches this configuration shortens the distance needed to drive the word lines, making clear what was only implied by the architecture already disclosed by the combination of Lin and Shukh. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to drive the multi-layer word lines, as in Ogawa, in the layered architecture of Lin and Shukh, with a reasonable expectation of success. All inventions are well known in the field of layered memory array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10 and the substantially similar limitations of new Claim 22, Shukh discloses the memory device of claim 9, wherein
each of the memory cells comprises a magnetic tunnel junction (Shukh, col.1:40-45).
Regarding Claim 11 and the substantially similar limitations of new Claim 24, Ogawa discloses the memory device of claim 9, wherein
the first circuit layer further comprises a second word line driver circuit, the second word line driver circuit of the first circuit layer is configured to drive a plurality of word lines disposed on the first circuit layer (Ogawa, ¶[02561]).
Regarding Amended Claim 12, Lin discloses the memory device of claim 9, wherein
a first word line is disposed on the second circuit layer, and
coupled to a first memory cell of the second circuit layer (Word line 403: Lin, Figure 4);
the first memory cell is coupled to a first bit line segment disposed on the second circuit layer (Lin, ¶[0024]);
the first circuit layer further comprises:
an amplifier circuit, wherein when the first word line is activated by the first word line driver circuit (Lin, ¶[0048]),
an input terminal of the amplifier circuit of the first circuit layer is arranged to receive a signal from the first memory cell of the second circuit layer (Lin, ¶[0048])
through the first bit line segment and one of the first conductive through via structures (Lin, ¶[0046]).
Regarding Amended Claim 13, Lin discloses the memory device of claim 9, wherein
a first word line is disposed on the second circuit layer, and coupled to a first memory cell of the second circuit layer (Word line 403: Lin, Figure 4);
the first memory cell is coupled to a first bit line segment disposed on the second circuit layer (Lin, ¶[0024]);
the first circuit layer further comprises:
a write driver circuit (Bit line driver: Shukh, col.6:63-66),
wherein when the first word line is activated by the first word line driver circuit, the write driver circuit of the first circuit layer is arranged to drive a data signal to the first memory cell through the first bit line segment (Writing via bit line driver: Shukh, col.5:11-14) and
one of the first conductive through via structures (Ogawa, Claim 8; See also Ogawa, ¶[0251]).
Regarding Amended Claim 14, Lin discloses the memory device of claim 9, wherein
a first word line is disposed on the second circuit layer, and coupled to a first memory cell of the second circuit layer (Word line 403: Lin, Figure 4); the first memory cell is coupled to a first bit line segment disposed on the second circuit layer (Lin, ¶[0024]);
the first circuit layer further comprises:
a bias driver circuit (Shukh, col.5:7-19),
wherein when the first word line is activated by the first word line driver circuit, the bias driver circuit of the first circuit layer is arranged to send a bias signal to the first memory cell through the first bit line segment and one of the first conductive through via structures (Shukh, col.5:7-19).
Regarding Claim 15 and the substantially similar limitations of new Claim 27, Lin discloses the memory device of claim 9, wherein
at least one of the first conductive through via structures comprises a through-silicon via (Lin, ¶[0019]).
Regarding Claim 16 and the substantially similar limitations of new Claim 23, Lin discloses the memory device of claim 9, wherein
at least one of the second conductive through via structures comprises a through-silicon via (Lin, ¶[0019]).
Regarding New Independent Claim 21, Lin discloses a memory device, comprising:
a plurality of circuit layers disposed one above another (Lin, ¶[0021]), each circuit layer comprising one or more memory cell arrays (Lin, ¶[0021]);
a plurality of first conductive through via structures penetrating through the circuit layers (Lin, ¶[0021]),
each first conductive through via structure electrically connecting bit line segments disposed on two or more of the circuit layers to form a respective bit line (Lin, ¶[0022]).
Lin discloses a three-dimensional memory circuit comprising multiple bonded layers interconnected by vias. Lin does expressly disclose the memory device comprising a word line driver circuit on a first layer, connected to and driving word lines on other layers through the vias. Shukh, however, discloses a layered memory array circuit including:
a word line driver circuit disposed on a first circuit layer of the circuit layers (Shukh, col.6:62-63 and Shukh, Figure 6);
a plurality of word lines formed on a second circuit layer of the circuit layers, the first circuit layer being different from the second circuit layer (Word lines 19-1-1 and 19-1-2: Shukh, Figure 5); and
a plurality of second conductive through via structures penetrating through the circuit layers and electrically connecting the word line driver circuit on the first circuit layer to the word lines on the second circuit layer (Shukh, col.6:60-62).
Once Lin has taught layering memory arrays connected by bias to connect bit line segments, and Shukh has taught layering word lines and word line circuitry in a similar manner, routing word line addresses and drive onto parallel is an obvious implementation choice. Doing so would allow repeating the word line driver on each layer, saving circuit space and cost. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to mimic the bit line driver and vias of Lin to implement the word line driver and vias of Shukh, with a reasonable expectation of success. Both inventions are well known in the field of stacked memory array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Lin and Shukh teach the underlying architecture wherein memory arrays are formed on different layers, with word line driver circuitry located on the first layer. Ogawa makes explicit the connecting configuration, wherein the word line driver circuit on the first circuit layer is configured to drive the word lines disposed on the second circuit layer according to a word line address input received via the plurality of second conductive through via structures (Ogawa, ¶[0251]).
Ogawa teaches this configuration shortens the distance needed to drive the word lines, making clear what was only implied by the architecture already disclosed by the combination of Lin and Shukh. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to drive the multi-layer word lines, as in Ogawa, in the layered architecture of Lin and Shukh, with a reasonable expectation of success. All inventions are well known in the field of layered memory array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding New Claim 25, Lin discloses the memory device of claim 21, wherein
each respective bit line comprises a plurality of bit line segments disposed on respective circuit layers and electrically connected through a respective first conductive through via structure (Lin, ¶[0018]), and wherein each bit line segment is coupled to a plurality of memory cells of a memory cell array of the circuit layer on which the bit line segment is disposed (Lin, ¶[0018]).
Regarding New Claim 26, Shukh discloses the memory device of claim 21, further comprising
a first word line on the second circuit layer and a second word line on the second circuit layer (Shukh, col.2:5-8),
the first word line being coupled to a first memory cell and the second word line being coupled to a second memory cell (Shukh, col.2:1-17),
wherein the word line driver circuit on the first circuit layer is arranged so that, for a given word line address input on the second conductive through via structures, activation of the first word line occurs without activation of the second word line (Shukh, col.5:8-11).
Claim(s) 17-20 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0130068 A1 to Chih-Yu Lin, et al. (hereafter Li), US 8,411,494 B2 to Alexander Mikhailovich Shukh (hereafter Shukh), and US 2017/0179153 A1 to Hiroyuki Ogawa, et al. (hereafter Ogawa) in view of US 6,765,835 B1 to Wayne Theel (hereafter Theel).
Regarding Amended Independent Claim 17, Lin discloses a method for operating a memory device, comprising:
the first circuit layer and the second circuit layer are stacked one over the other in the memory device (Lin, ¶[0021]),
the first memory cell is coupled to the first word line and the first bit line (Lin, ¶[0021]);
the second memory cell is coupled to the second word line and the second bit line (Lin, ¶[0021]).
Lin discloses a three-dimensional memory circuit comprising multiple bonded layers interconnected by vias. Lin does expressly disclose the memory device comprising a word line driver circuit on a first layer, connected to and driving word lines on other layers through the vias. Shukh, however, discloses a layered memory array circuit including:
the first conductive through via structure is formed between the first circuit layer and the second circuit layer (Shukh, col.6:60-62), and
wherein the second conductive through via structure is formed between the first circuit layer and the second circuit layer (Shukh, col.6:60-62), and
Once Lin has taught layering memory arrays connected by bias to connect bit line segments, and Shukh has taught layering word lines and word line circuitry in a similar manner, routing word line addresses and drive onto parallel is an obvious implementation choice. Doing so would allow repeating the word line driver on each layer, saving circuit space and cost. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to mimic the bit line driver and vias of Lin to implement the word line driver and vias of Shukh, with a reasonable expectation of success. Both inventions are well known in the field of stacked memory array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Lin and Shukh teach the underlying architecture wherein memory arrays are formed on different layers, with word line driver circuitry located on the first layer. Ogawa makes explicit the connecting configuration, that is:
utilizing a word line driver circuit disposed on a first circuit layer to drive a first word line disposed on a second circuit layer through a first conductive through via structures (Ogawa, ¶[0251])
utilizing the word line driver circuit disposed on the first circuit layer to drive a second word line disposed on the second circuit layer through a second conductive through via structure (Ogawa, ¶[0251]).
Ogawa teaches this configuration shortens the distance needed to drive the word lines, making clear what was only implied by the architecture already disclosed by the combination of Lin and Shukh. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to drive the multi-layer word lines, as in Ogawa, in the layered architecture of Lin and Shukh, with a reasonable expectation of success. All inventions are well known in the field of layered memory array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Lin does not teach the amplifier being linked to the first and second layers. Shukh, and Ogawa do not mention an amplifier circuit at all. Theel, however, teaches a memory array wherein:
a first signal of a first memory cell of the memory device being generated on a first bit line in bit line in response to activation of the first word line (The upper and lower sense lines connected to the same differential amplifier: Theel, col.6:19-25),
a second signal of a second memory cell of the memory device being generated on a second bit line in bit line in response to activation of the second word line (The upper and lower sense lines connected to the same differential amplifier: Theel, col.6:19-25),
generating an output signal of an amplifier circuit according to the first signal and the second signal, wherein the amplifier circuit is coupled to the first bit line and the second bit line (The upper and lower sense lines connected to the same differential amplifier: Theel, col.6:19-25).
This configuration saves on circuit space and allows for a differential between multiple circuits using a single amplifier and (Theel, col.6:19-50). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the combined amplifier of Theel with the layered memory array architecture of the other art, with a reasonable expectation of success. All inventions are well known in the field of layered memory architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Lin discloses the method of claim 17, wherein
the amplifier circuit is disposed on the first circuit layer (Lin, ¶[0048]).
Regarding Claim 19, Lin discloses the method of claim 17, wherein
the amplifier circuit is disposed on the second circuit layer (Lin, ¶[0048]).
Regarding Claim 20, Theel discloses the method of claim 17, wherein generating the output signal of the amplifier circuit according to the first signal and the second signal comprises:
generating the output signal by comparing the first signal with the second signal (Theel, col.6:19-25).
Regarding New Claim 28, Lin and Ogawa disclose the memory device of claim 21, further comprising
the word line driver circuit on the first circuit layer (Ogawa, ¶[0251]) is configured to drive a first word line and a second word line disposed on the second circuit layer via respective second conductive through via structures (Ogawa, ¶[0251]); and
each of the first bit line and the second bit line comprises bit line segments disposed on the circuit layers and electrically connected through respective first conductive through via structures (Lin, ¶[0018]).
Lin does not teach the amplifier being linked to the first and second layers. Shukh, and Ogawa do not mention an amplifier circuit at all. Theel, however, teaches a memory array wherein:
an amplifier circuit having a first input terminal and a second input terminal, wherein (Sense amplifier 132: Theel, Figure 1):
the first input terminal is coupled to the first bit line, and the second input terminal is coupled to the second bit line (Theel, Figure 1);
a first signal of a first memory cell of the memory device is generated on a first bit line in response to activation of the first word line (The upper and lower sense lines connected to the same differential amplifier: Theel, col.6:19-25);
a second signal of a second memory cell of the memory device is generated on a second bit line in response to activation of the second word line (The upper and lower sense lines connected to the same differential amplifier: Theel, col.6:19-25);
the amplifier circuit is configured to generate an output signal based on a comparison of the first signal and the second signal (Theel, col.6:19-25); and
This configuration saves on circuit space and allows for a differential between multiple circuits using a single amplifier and (Theel, col.6:19-50). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the combined amplifier of Theel with the layered memory array architecture of the other art, with a reasonable expectation of success. All inventions are well known in the field of layered memory architecture and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8,054,665 B2 to Seung-eon Ahn: Disclosing a tiered memory array stack with divided bit lines and word lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/PHO M LUU/Primary Examiner, Art Unit 2824
Prosecution Insights