Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, the claim introduces “a hard mask film” and subsequently refers to “the hard mask film.” However, the claim later recites “the WSi hard mask film” without previously introducing the WSi hard mask film as such. It is therefore unclear whether “the WSi hard mask film” is intended to refer to the previously recited “hard mask film.” Accordingly, the recitation of “the WSi hard mask film” lacks clear antecedent basis.
Claims 3 and 6 likewise recite “the WSi hard mask film” without clear antecedent basis to that specific term.
Claims 2–10 is rejected under 35 U.S.C. 112(b) by virtue of their dependency from claim 1, which is rejected above.
Regarding claim 11, the claim likewise introduces “a hard mask film” and subsequently refers to “the hard mask film.” However, the claim later recites “the WSi hard mask film” without previously introducing the WSi hard mask film as such. It is therefore unclear whether “the WSi hard mask film” is intended to refer to the previously recited “hard mask film.” Accordingly, the recitation of “the WSi hard mask film” lacks clear antecedent basis.
Claims 13 and 16 likewise recite “the WSi hard mask film” without clear antecedent basis to that specific term.
Claims 12–20 are rejected under 35 U.S.C. 112(b) by virtue of their dependency from claim 11, which is rejected above.
Claims 1 and 11 recite determining a film stress of the hard mask film and subsequently recite performing WSi deposition to form the hard mask film. The claims further recite determining an annealing time based on the determined film stress of the WSi hard mask film. the determined film stress is linked to “the hard mask” and the determined time period refers to the determined film stress as the stress of the WSi hard mask so its unclear of the “time period” is linked to the “hard mask” film stress or the “WSi hard mask” film stress. Applicant is required to clarify the relationship between the initially recited film stress, formation of the WSi hard mask film, and the film stress subsequently used to determine the annealing time.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2015/0187579 A1) in view of Toshima et al. (US 2020/0266063 A1), further in view of Veber et al. (US 2023/0298896 A1), and further in view of Nittala et al. (US 2022/0262643 A1).
Regarding claim 1, Lin teaches a method of forming a hard mask film over a semiconductor device (Lin forms a stress-controlled hard mask over a semiconductor substrate during fabrication of a semiconductor device; paragraphs [0012]-[0017] and claim 15).
Lin further teaches determining a film stress of the hard mask film based on an internal stress of the semiconductor device (Lin determines the type and magnitude of stress associated with the semiconductor structure that is expected to act on the hard mask and determines a desired internal stress of the hard mask that counterbalances the determined stress; paragraphs [0012]-[0017]).
Lin does not expressly teach performing a tungsten silicide (WSi) deposition over the semiconductor device to form the hard mask film.
Toshima teaches performing a tungsten silicide (WSi) deposition over the semiconductor device to form the hard mask film (Toshima teaches tungsten silicide as a hard-mask material for semiconductor plasma etching and further teaches forming a hard mask containing tungsten and silicon over a silicon-containing film by sputtering; paragraphs [0003]-[0010] and [0024]-[0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lin to form the hard mask as a tungsten silicide (WSi) hard mask as taught by Toshima because Toshima teaches tungsten silicide as a known hard-mask material suitable for plasma etching semiconductor structures, and simple substitution of one known hard-mask material for another to obtain predictable results is obvious, see MPEP § 2141 III(B).
Modified Lin does not expressly teach performing the tungsten silicide (WSi) deposition at a cryogenic temperature.
Veber teaches performing deposition of a metal-containing film at a cryogenic temperature (Veber deposits a metal-containing protective film in a plasma etch chamber at a deposition temperature that may be the same or similar to the etch temperature, including temperatures between about −100°C and 0°C; identifies tungsten as an exemplary metal and teaches that the deposited protective film may be a metal silicide; and expressly teaches forming the protective film at a cryogenic temperature, for example between about −100°C and about −10°C; paragraphs [0059], [0061], and [0064]). Veber further teaches that such low-temperature deposition permits formation of the protective film at temperatures comparable to semiconductor etching temperatures without requiring additional substrate heating controls (paragraphs [0063]-[0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin to perform the WSi hard-mask deposition at a cryogenic temperature as taught by Veber because Veber teaches forming metal-containing films at cryogenic semiconductor-processing temperatures without requiring additional substrate heating controls. Applying Veber’s known low-temperature deposition technique to the WSi hard-mask deposition of modified Lin would have been the use of a known technique to improve a similar semiconductor-processing method in the same way, see MPEP § 2141 III(C).
Modified Lin does not expressly teach determining a time period of an annealing process to be performed based on the determined film stress of the WSi hard mask film and performing the annealing process to the WSi hard mask film based on the determined time period.
Nittala teaches determining a time period of an annealing process to be performed based on the determined film stress of the hard mask film (Nittala teaches using measured film stress and/or substrate bow to determine an optimized anneal time for obtaining a desired hard-mask film stress condition; paragraph [0024]).
Nittala further teaches performing the annealing process to the hard mask film based on the determined time period (Nittala deposits one or more hard-mask layers and subsequently performs rapid thermal annealing for the selected anneal time, thereby altering the stress of the deposited hard-mask layers; paragraphs [0050]-[0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin to determine an annealing time based on the hard-mask film stress and perform the annealing process for the determined time as taught by Nittala because Nittala teaches determining and using an anneal time to obtain a desired hard-mask stress and reduce undesirable compressive stress and substrate bow, and use of a known technique to improve similar methods in the same way is obvious, see MPEP § 2141 III(C).
Regarding claim 2, the modified method of Lin teaches the limitations of claim 1 as discussed above. Lin further teaches wherein the determined film stress of the hard mask film is complementary to the internal stress of the semiconductor device (Lin teaches determining the desired internal stress of the hard mask such that it counterbalances the stress associated with the semiconductor structure, including a tensile internal stress of the hard mask to counterbalance a compressive stress and a compressive internal stress of the hard mask to counterbalance a tensile stress; paragraphs [0012]-[0017] and claims 5–6).
Regarding claim 3, the modified method of Lin teaches the limitations of claim 1 as discussed above. Toshima further teaches performing a patterning process to the WSi hard mask film and performing an etching process to the semiconductor device based on the patterned WSi hard mask film (Toshima forms a pattern in the tungsten-and-silicon hard mask HM by photolithography and plasma etching, and teaches that the patterned hard mask HM is used as a mask for plasma etching the underlying silicon-containing film SF; paragraphs [0025] and [0053]).
Regarding claim 5, the modified method of Lin teaches the limitations of claim 1 as discussed above. Lin further teaches wherein the semiconductor device comprises a substrate and a film stack formed over the substrate (Lin teaches a semiconductor substrate having an insulating layer formed thereover, with the hard mask formed over the insulating layer; paragraphs [0039]-[0041] and claim 19).
Regarding claim 6, the modified method of Lin teaches the limitations of claim 5 as discussed above. Toshima further teaches wherein the WSi hard mask film is formed over the film stack (Toshima teaches a target object including a substrate and an overlying silicon-containing film, which may be a multilayer film, and forms the tungsten-and-silicon hard mask over the silicon-containing film; paragraphs [0024]-[0026]).
Regarding claim 10, the modified method of Lin teaches the limitations of claim 1 as discussed above. Nittala further teaches wherein the WSi deposition and the annealing process are performed in different chambers (Nittala teaches a deposition chamber configured to deposit the hard-mask layer and a separate anneal chamber configured to perform the rapid thermal anneal operation, with a transfer chamber coupled to the deposition chamber and the anneal chamber; paragraph [0017] and claim 19).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nittala et al. in view of Lin et al., further in view of Toshima et al., further in view of Veber et al. as applied to claim 5 above, and further in view of Dole et al. (US 2020/0126804 A1).
Regarding claim 7, the modified method of Lin teaches the limitations of claim 5 as discussed above.
The modified method of Lin does not expressly teach wherein the film stack comprises alternating insulating layers and conducting layers.
Dole teaches wherein the film stack comprises alternating insulating layers and conducting layers (Dole teaches a film stack used in fabricating a three-dimensional NAND structure comprising alternating layers of silicon oxide and polysilicon; paragraphs [0005] and [0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin such that the film stack comprises alternating insulating layers and conducting layers as taught by Dole because Dole teaches alternating silicon oxide and polysilicon layers as a known film-stack configuration for fabricating three-dimensional NAND semiconductor structures. Applying Dole’s known film-stack configuration to the semiconductor device of modified Lin would have been the use of a known structure in a similar semiconductor device to obtain the predictable result of providing a multilayer three-dimensional memory structure, see MPEP § 2141 III(C).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Toshima et al., further in view of Veber et al., further in view of Nittala et al. as applied to claim 5 above, and further in view of Baraskar et al. (US 9,779,948 B1).
Regarding claim 8, the modified method of Lin teaches the limitations of claim 5 as discussed above.
The modified method of Lin does not expressly teach wherein the film stack comprises alternating insulating layers and sacrificial layers.
Baraskar teaches wherein the film stack comprises alternating insulating layers and sacrificial layers (Baraskar teaches depositing alternating silicon oxide and silicon nitride layers above a semiconductor substrate, wherein the silicon nitride layers are sacrificial layers and the silicon oxide layers are insulating layers; col. 11, ll. 40–52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin such that the film stack comprises alternating insulating layers and sacrificial layers as taught by Baraskar because Baraskar teaches such alternating insulating and sacrificial layers as a known stack configuration for fabricating three-dimensional NAND semiconductor structures, wherein the sacrificial layers are subsequently replaced by conductive material to form word lines. The modification would have amounted to the use of a known structure in a similar semiconductor device to obtain the predictable result of providing a multilayer three-dimensional memory structure, see MPEP § 2141 III(C).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Toshima et al., further in view of Veber et al., further in view of Nittala et al. as applied to claim 1 above, and further in view of Chern et al. (US 6,500,742 B1).
Regarding claim 9, the modified method of Lin teaches the limitations of claim 1 as discussed above.
The modified method of Lin does not expressly teach wherein the WSi deposition and the annealing process are performed in a same chamber.
Chern teaches wherein the deposition and the annealing process are performed in a same chamber (Chern teaches depositing a layer of material on a semiconductor wafer and subsequently annealing the deposited material, with the deposition and annealing performed in a single chamber without removing the wafer; Chern further teaches that such in-situ processing reduces contamination by decreasing transfers between different pieces of manufacturing equipment and reduces the number of expensive pieces of manufacturing equipment required; column 3, lines 25–39; column 4, lines 21–41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin to perform the WSi deposition and the annealing process in the same chamber as taught by Chern because Chern teaches that performing deposition and annealing in the same chamber reduces contamination associated with transferring the semiconductor wafer between different processing equipment and reduces the amount of processing equipment required, and use of a known technique to improve similar methods in the same way is obvious, see MPEP § 2141 III(C).
Claims 11-13, 15-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nittala et al. (US 2022/0262643 A1) in view of Lin et al. (US 2015/0187579 A1), further in view of Toshima et al. (US 2020/0266063 A1), and further in view of Veber et al. (US 2023/0298896 A1).
Regarding claim 11, Nittala teaches a semiconductor processing system for forming a hard mask film over a semiconductor device, the semiconductor processing system comprising a controller configured to perform semiconductor-processing operations (Nittala teaches a system including a deposition chamber, an anneal chamber, a transfer chamber, and a controller comprising instructions that cause deposition of one or more hard-mask layers and subsequent rapid thermal annealing; claim 19).
Nittala further teaches a controller configured to determine a time period of an annealing process to be performed based on a determined film stress of the hard mask film and perform the annealing process to the hard mask film based on the determined time period (Nittala teaches using measured film stress and/or substrate bow to determine an optimized anneal time for obtaining a desired hard-mask film stress condition; paragraphs [0023]-[0024], and subsequently performing rapid thermal annealing for the determined anneal time to alter the stress of the hard-mask layer; paragraphs [0051]-[0055]).
Nittala does not expressly teach the controller being configured to determine a film stress of the hard mask film based on an internal stress of the semiconductor device.
Lin teaches determining a film stress of the hard mask film based on an internal stress of the semiconductor device (Lin determines the type and magnitude of stress associated with the semiconductor structure that is expected to act on the hard mask and determines a desired internal stress of the hard mask that counterbalances the determined stress; paragraphs [0012]-[0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor processing system of Nittala such that the controller determines the hard-mask film stress based on stress associated with the semiconductor structure as taught by Lin because Lin teaches controlling hard-mask stress to counterbalance stress associated with the semiconductor structure, while Nittala already uses its controller to optimize hard-mask processing based on film stress and substrate bow. Applying Lin’s known stress-control technique in Nittala’s controller-controlled hard-mask processing system would have been the use of a known technique to improve a similar system in the same way, see MPEP § 2141 III(C).
Modified Nittala does not expressly teach performing a tungsten silicide (WSi) deposition over the semiconductor device to form the hard mask film.
Toshima teaches performing a tungsten silicide (WSi) deposition over the semiconductor device to form the hard mask film (Toshima teaches tungsten silicide as a hard-mask material for semiconductor plasma etching and further teaches forming a hard mask containing tungsten and silicon over a silicon-containing film by sputtering; paragraphs [0003]-[0010] and [0024]-[0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify modified Nittala to form the hard mask as a tungsten silicide (WSi) hard mask as taught by Toshima because Toshima teaches tungsten silicide as a known hard-mask material suitable for plasma etching semiconductor structures, and simple substitution of one known hard-mask material for another to obtain predictable results is obvious, see MPEP § 2141 III(B).
Modified Nittala does not expressly teach performing the tungsten silicide (WSi) deposition at a cryogenic temperature.
Veber teaches performing deposition of a metal-containing film at a cryogenic temperature (Veber deposits a metal-containing protective film in a plasma etch chamber at a deposition temperature that may be the same or similar to the etch temperature, including temperatures between about −100°C and 0°C; identifies tungsten as an exemplary metal and teaches that the deposited protective film may be a metal silicide; and expressly teaches forming the protective film at a cryogenic temperature, for example between about −100°C and about −10°C; paragraphs [0059], [0061], and [0064]). Veber further teaches that such low-temperature deposition permits formation of the protective film at temperatures comparable to semiconductor etching temperatures without requiring additional substrate heating controls (paragraphs [0063]-[0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify modified Nittala to perform the WSi hard-mask deposition at a cryogenic temperature as taught by Veber because Veber teaches forming metal-containing films at cryogenic semiconductor-processing temperatures without requiring additional substrate heating controls. Applying Veber’s known low-temperature deposition technique to the WSi hard-mask deposition of modified Nittala would have been the use of a known technique to improve a similar semiconductor-processing system in the same way, see MPEP § 2141 III(C).
Regarding claim 12, the modified method of Lin teaches the limitations of claim 11 as discussed above. Lin further teaches wherein the determined film stress of the hard mask film is complementary to the internal stress of the semiconductor device (Lin teaches determining the desired internal stress of the hard mask such that it counterbalances the stress associated with the semiconductor structure, including a tensile internal stress of the hard mask to counterbalance a compressive stress and a compressive internal stress of the hard mask to counterbalance a tensile stress; paragraphs [0012]-[0017] and claims 5–6).
Regarding claim 13, the modified method of Lin teaches the limitations of claim 11 as discussed above. Toshima further teaches performing a patterning process to the WSi hard mask film and performing an etching process to the semiconductor device based on the patterned WSi hard mask film (Toshima forms a pattern in the tungsten-and-silicon hard mask HM by photolithography and plasma etching, and teaches that the patterned hard mask HM is used as a mask for plasma etching the underlying silicon-containing film SF; paragraphs [0025] and [0053]).
Regarding claim 15, the modified method of Lin teaches the limitations of claim 11 as discussed above. Lin further teaches wherein the semiconductor device comprises a substrate and a film stack formed over the substrate (Lin teaches a semiconductor substrate having an insulating layer formed thereover, with the hard mask formed over the insulating layer; paragraphs [0039]-[0041] and claim 19).
Regarding claim 16, the modified method of Lin teaches the limitations of claim 15 as discussed above. Toshima further teaches wherein the WSi hard mask film is formed over the film stack (Toshima teaches a target object including a substrate and an overlying silicon-containing film, which may be a multilayer film, and forms the tungsten-and-silicon hard mask over the silicon-containing film; paragraphs [0024]-[0026]).
Regarding claim 20, the modified method of Lin teaches the limitations of claim 11 as discussed above. Nittala further teaches wherein the WSi deposition and the annealing process are performed in different chambers (Nittala teaches a deposition chamber configured to deposit the hard-mask layer and a separate anneal chamber configured to perform the rapid thermal anneal operation, with a transfer chamber coupled to the deposition chamber and the anneal chamber; paragraph [0017] and claim 19).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Nittala et al. in view of Lin et al., further in view of Toshima et al., further in view of Veber et al. as applied to claim 15 above, and further in view of Dole et al. (US 2020/0126804 A1).
Regarding claim 17, the modified method of Lin teaches the limitations of claim 15 as discussed above.
The modified method of Lin does not expressly teach wherein the film stack comprises alternating insulating layers and conducting layers.
Dole teaches wherein the film stack comprises alternating insulating layers and conducting layers (Dole teaches a film stack used in fabricating a three-dimensional NAND structure comprising alternating layers of silicon oxide and polysilicon; paragraphs [0005] and [0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin such that the film stack comprises alternating insulating layers and conducting layers as taught by Dole because Dole teaches alternating silicon oxide and polysilicon layers as a known film-stack configuration for fabricating three-dimensional NAND semiconductor structures. Applying Dole’s known film-stack configuration to the semiconductor device of modified Lin would have been the use of a known structure in a similar semiconductor device to obtain the predictable result of providing a multilayer three-dimensional memory structure, see MPEP § 2141 III(C).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Toshima et al., further in view of Veber et al., further in view of Nittala et al. as applied to claim 15 above, and further in view of Baraskar et al. (US 9,779,948 B1).
Regarding claim 18, the modified method of Lin teaches the limitations of claim 5 as discussed above.
The modified method of Lin does not expressly teach wherein the film stack comprises alternating insulating layers and sacrificial layers.
Baraskar teaches wherein the film stack comprises alternating insulating layers and sacrificial layers (Baraskar teaches depositing alternating silicon oxide and silicon nitride layers above a semiconductor substrate, wherein the silicon nitride layers are sacrificial layers and the silicon oxide layers are insulating layers; col. 11, ll. 40–52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified method of Lin such that the film stack comprises alternating insulating layers and sacrificial layers as taught by Baraskar because Baraskar teaches such alternating insulating and sacrificial layers as a known stack configuration for fabricating three-dimensional NAND semiconductor structures, wherein the sacrificial layers are subsequently replaced by conductive material to form word lines. The modification would have amounted to the use of a known structure in a similar semiconductor device to obtain the predictable result of providing a multilayer three-dimensional memory structure, see MPEP § 2141 III(C).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Toshima et al., further in view of Veber et al., further in view of Nittala et al. as applied to claim 11 above, and further in view of Chern et al. (US 6,500,742 B1).
Regarding claim 9, the modified method of Lin teaches the limitations of claim 11 as discussed above.
The modified semiconductor processing system of Nittala does not expressly teach wherein the WSi deposition and the annealing process are performed in a same chamber.
Chern teaches wherein the deposition and the annealing process are performed in a same chamber (Chern teaches depositing a layer of material on a semiconductor wafer and subsequently annealing the deposited material, with the deposition and annealing performed in a single chamber without removing the wafer; Chern further teaches that such in-situ processing reduces contamination by decreasing transfers between different pieces of manufacturing equipment and reduces the number of expensive pieces of manufacturing equipment required; column 3, lines 25–39; column 4, lines 21–41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the modified semiconductor processing system of Nittala to perform the WSi deposition and the annealing process in the same chamber as taught by Chern because Chern teaches that performing deposition and annealing in the same chamber reduces contamination associated with transferring the semiconductor wafer between different processing equipment and reduces the amount of processing equipment required, and use of a known technique to improve similar systems in the same way is obvious, see MPEP § 2141 III(C).
Allowable Subject Matter
Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4, the prior art of record fails to teach or suggest, alone or in combination with other prior art, performing the tungsten silicide (WSi) deposition at a cryogenic temperature between 50 K and 150 K in the context of the remaining limitations of claims 1 and 4.
Veber is considered the closest prior art with respect to cryogenic deposition. Veber teaches depositing a metal-containing protective film at low or cryogenic temperatures, including deposition temperatures from about −100°C to −10°C, and further teaches tungsten as an exemplary metal and metal silicides as possible compositions of the protective film (paragraphs [0059], [0061], and [0064]). However, Veber does not teach or suggest depositing tungsten silicide at a temperature between 50 K and 150 K. Veber’s expressly disclosed cryogenic range of about −100°C to −10°C corresponds to approximately 173 K to 263 K, which is above the claimed range.
Toshima teaches tungsten silicide as a hard-mask material for semiconductor plasma etching and further teaches forming a hard mask containing tungsten and silicon over a silicon-containing film, but does not teach forming a tungsten silicide hard
mask at a temperature between 50 K and 150 K (paragraphs [0003]-[0010] and [0024]-[0026]).
Accordingly, although the prior art teaches tungsten-silicide hard masks and separately teaches cryogenic deposition of metal-containing films, the prior art of record does not teach or suggest performing the tungsten silicide deposition at a cryogenic temperature between 50 K and 150 K as required by claim 4.
As to claim 14, the prior art of record fails to teach or suggest, alone or in combination with other prior art, a semiconductor processing system configured to perform the tungsten silicide (WSi) deposition at a cryogenic temperature between 50 K and 150 K in the context of the remaining limitations of claims 11 and 14.
Veber is considered the closest prior art with respect to cryogenic deposition. Veber teaches depositing a metal-containing protective film at low or cryogenic temperatures, including deposition temperatures from about −100°C to −10°C, and further teaches tungsten as an exemplary metal and metal silicides as possible compositions of the protective film (paragraphs [0059], [0061], and [0064]). However, Veber does not teach or suggest depositing tungsten silicide at a temperature between 50 K and 150 K. Veber’s expressly disclosed cryogenic range of about −100°C to −10°C corresponds to approximately 173 K to 263 K, which is above the claimed range.
Toshima teaches tungsten silicide as a hard-mask material for semiconductor plasma etching and further teaches forming a hard mask containing tungsten and silicon over a silicon-containing film, but does not teach forming a tungsten silicide hard mask at a temperature between 50 K and 150 K (paragraphs [0003]-[0010] and [0024]-[0026]).
Accordingly, although the prior art teaches tungsten-silicide hard masks and separately teaches cryogenic deposition of metal-containing films, the prior art of record does not teach or suggest a semiconductor processing system configured to perform the tungsten silicide deposition at a cryogenic temperature between 50 K and 150 K as required by claim 14.
Conclusion
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/JONATHAN L CARTER/Examiner, Art Unit 1713
/ERIN F BERGNER/Primary Examiner, Art Unit 1713
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