DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 08/24/2026 is acknowledged. The traversal is on the ground(s) that there is no search burden. This is not found persuasive because mutually independent inventions are claimed that have divergent search requirements.
The requirement is still deemed proper and is therefore made FINAL.
Claim 9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 08/24/2026.
Drawings
The drawings are objected to because the reference characters of figures 2, 3, 4, and 5 are illegible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw, US 9646974 B1.
As to claim 1, Liaw discloses a method of manufacturing a memory circuit (see Fig 2), the method comprising:
forming active regions (see Fig 4 Refs Pwell1, Nwell, and Pwell2, and Col 3 Lines 63-15) in a semiconductor substrate (see Fig 3 Ref Core and Cols 3-4 Lines 63-15), wherein
the active regions each define a long axis (see Fig 4 Refs 521-524 and 531-534, and Col 4-5 Lines 62-2) that extends in a first direction (see annotated image of Liaw Fig 4 below), at least some of the active regions (see Fig 4 Refs 521-524) corresponding to a first dual-port memory cell (see Fig 4 Refs PG1 and PG3 and Col 3 Lines 5-14) and other ones of the active regions (see 4 Refs 531-534) corresponding to a second dual-port memory cell (see Fig 4 Refs PG2 and PG4 and Col 3 Lines 5-14) that is adjacent (see Fig 4) to the first dual-port memory cell;
forming gate electrodes (see Fig 4 Refs 541-543 and 551-553) over the active regions, wherein
the gate electrodes extend in a second direction perpendicular (see annotated image of Liaw Fig 4 below) to the first direction and include subsets (see Fig 4 Refs 541-543 and 551-553) in each of the first and second dual-port memory cells;
forming bit line landing pads (see Fig 4 Refs 161-164) in a first metal layer (see Fig 4 Ref M1) above (see Fig 3 Refs M1 and Gate_CO) the gate electrodes, pairs of the bit line landing pads (see Fig 4 Refs 161 + 163, and 162 + 164) being aligned in the first direction and separated by local interconnects (see Fig 4 Refs 591 and 592); and
forming word lines (see Fig 5A Ref WL1) in a second metal layer (see Fig 5A Ref M2 and Fig 3 Ref M2) that is above the first metal layer, wherein
the word lines extend in the second direction (see annotated image of Liaw Fig 4 below).
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As to claim 2, Liaw discloses the method of claim 1, wherein
the forming the word lines in the second metal layer comprises forming bit line landing pads (see Fig 5A Ref 221) in the second metal layer above the bit line landing pads formed in the first metal layer.
As to claim 3, Liaw discloses the method of claim 2, further comprising:
forming bit lines in a third metal layer (see Fig 3 Ref M4 and Col 10 Lines 4-14) above the bit line landing pads formed in the second metal layer, wherein the bit lines extend in the first direction.
As to claim 4, Liaw discloses the method of claim 3, further comprising:
forming additional word lines (see Fig 5A Ref WL2) in a fourth metal layer (see Fig 3 Ref M3 and Col 8 Lines 58-65) above and electrically connected to the word lines formed in the second metal layer.
As to claim 5, Liaw discloses the method of claim 1, wherein
each of the local interconnects comprises an internal node of the corresponding first or second dual-port memory cell (see Fig 2 Refs N1, N2, N3, and N4).
As to claim 6, Liaw discloses the method of claim 1, wherein
the forming the word lines in the second metal layer comprises electrically coupling each of the word lines to two of the gate electrodes in each of the first dual-port memory cell and the second dual-port memory cell (see Fig 2 Ref WL1; Electrical coupling does not imply directly connected.).
As to claim 7, Liaw discloses the method of claim 1, wherein
the forming the active regions, the gate electrodes, the bit line landing pads, and the word lines comprises configuring the first and second dual-port memory cells as part of a dual-port memory array (see Fig 8 Ref 800).
As to claim 8, Liaw discloses the method of claim 1, wherein
the forming the active regions and the gate electrodes comprises configuring the active regions and the gate electrodes as fin field effect transistors (FinFETs) (see Col 1 Lines 20-28).
As to claim 10, Liaw discloses the method of claim 1, wherein
the at least some of the active regions corresponding to the first dual-port memory cell and the other ones of the active regions corresponding to the second dual-port memory cell comprise the first and second dual-port memory cells being mirror images of each other and sharing a conductive line in the first metal layer (see Fig 4 Refs 531-534).
Allowable Subject Matter
Claim(s) 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 11):
forming, in a first metal layer above the plurality of gate electrodes, a first-to-second pull-down transistor interconnect positioned between first and second bit line landing pads and a third-to-fourth pull-down transistor interconnect positioned between third and fourth bit line landing pads.
The prior art does not appear to disclose (as recited in claim 17):
a first-to-second pull-down transistor interconnect positioned between first and second bit line landing pads, a third-to-fourth pull-down transistor interconnect positioned between third and fourth bit line landing pads, a first conductor electrically connected to the first gate electrodes of the first and second pass gates, and a second conductor electrically connected to the second gate electrodes of the third and fourth pass gates.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fujiwara, US 20150357279 A1 does not appear to disclose a third-to-fourth pull-down transistor interconnect.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 09/15/2026
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