DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 25, 2026 has been entered.
Status of the Claims
Group I and Species 2, was elected.
Amendment filed June 25, 2026 is acknowledged. New claim 30 has been added. Claim 9 has been cancelled. Claims 1, 3-5, 7-8, 10, 21 and 27 have been amended. Claims 1-8, 10-11 and 21-30 are pending.
Action on merits of the Elected Group I, Species 2, claims 1-8, 10-11 and 21-30 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 7 and 10 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Amended claim 7 recites: the semiconductor structure of claim 1, wherein the first doped region has a first lower boundary, the first oxide layer has a second lower boundary, and the first polysilicon structure has a third lower boundary.
Any layer inherently has an upper boundary and a lower boundary.
Therefore, the limitation of claim 7 fails to further limit the boundaries of the first doped region, the first oxide layer and the first polysilicon structure of claim 1.
Amended claim 10 recites: the semiconductor structure of claim 1, wherein the first doped region has a first lower boundary, the first oxide layer has a second lower boundary, the lower portion of the first polysilicon structure has a fourth lower boundary, and the upper portion of the first polysilicon structure has a fifth lower boundary.
As discussed in claim 7 above, any layer inherently has an upper boundary and a lower boundary.
Therefore, the limitation of claim 10 fails to further limit the boundaries of the first doped region, the first oxide layer and the upper and lower portions of first polysilicon structure of claim 1.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-8, 10-11 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over YEN et al. (2014/0145207) in view of HIRLER (US. Pub. No. 2016/0020315) both of record, and NAKANO (US. Patent No. 8,283,721).
With respect to claim 1, YEN teaches a semiconductor structure substantially as claimed including:
a substrate (30) comprising a first surface (301) and a second surface (302) positioned on an opposite side of the substrate;
a first trench structure (30a) extending from the first surface toward the second surface, wherein the first trench structure (30a) comprises a first polysilicon structure (39) and a first oxide layer (35) surrounding the first polysilicon structure (39);
a shielding metal layer (37) located on the first surface (301) of the substrate and covering the first trench structure (30a);
a first conductive layer (38) disposed on the shielding metal layer (37) and entirely isolated from the first oxide layer (35) by the shielding metal layer (37);
a second conductive layer (not shown) disposed on the second surface (302) of the substrate; and
wherein the first polysilicon structure (30a) comprises a lower portion and an upper portion connected to the lower portion and extending from the first surface to the lower portion along a first direction,
a width of the upper portion along a second direction is greater than a width of the lower portion along the second direction,
the first direction is substantially orthogonal to the second direction,
the first oxide layer (35) comprises a bottom wall portion below the first polysilicon structure (39), and a sidewall portion surrounding the lower portion of the first polysilicon structure (39)
a thickness of the bottom wall portion along the first direction and a thickness of the sidewall portion along the second direction. (See FIG. 3).
Thus, YEN is shown to teach all the features of the claim with the exception of explicitly disclosing a thickness of the bottom wall portion along the first direction being greater than a thickness of the sidewall portion along the second direction; a first doped region adjacent to the bottom wall portion of the first oxide layer; and a maximum width of the first doped region is less than a width of a bottom of the first trench structure.
However, HIRLER teaches a semiconductor structure including:
a first trench structure (614) extending from a first surface (604) of a substrate toward a second surface (606), wherein the first trench structure comprises a first polysilicon structure (622) and a first oxide layer (626) surrounding the first polysilicon structure (622),
wherein the first polysilicon structure (622) comprises a lower portion and an upper portion connected to the lower portion and extending from the first surface (604) to the lower portion along a first direction,
the first oxide layer (626) comprises a bottom wall portion (630) below the first polysilicon structure (622), and a sidewall portion (628) surrounding the lower portion of the first polysilicon structure (622), and
a thickness of the bottom wall portion (630) along the first direction is greater than a thickness of the sidewall portion (628) along the second direction; and
a first doped region (636) in the substrate, wherein the first doped region (636) is adjacent to the bottom wall portion (630) of the first oxide layer (626) and separated from the first polysilicon structure (622), and wherein a maximum width of the first doped region (636) and a width of a bottom of the first trench structure (614). (See FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first dielectric layer of YEN having the thickness of the bottom wall portion along the first direction being greater than the thickness of the sidewall portion along the second direction as taught by HILER to improve the ability of the first oxide layer to withstand breakdown under high reverse voltage conditions; and due to the first doped region adjacent to the bottom wall portion the on-resistance remain nearly unchanged.
Further, NAKANO teaches a semiconductor structure including:
a first doped region (15) in the substrate, wherein the first doped region (15) is adjacent to bottom wall portion of first oxide layer (3) and separated from first polysilicon structure (41), and wherein a maximum width of the first doped region (15) is less than a width of a bottom of the first trench structure (3). (See FIG. 7).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first doped region of YEN, in view of HIRLER, having the maximum width being less than the width of the bottom of the first trench structure as taught by NAKANO to suppress an increase in on-resistance.
With respect to claim 2, a top surface of the first polysilicon structure (39) and a top surface of the first oxide layer (35) of YEN are coplanar with the first surface (301).
With respect to claim 3, in view of NAKANO, the semiconductor structure further comprises:
a second trench structure (3) extending from the first surface toward the second surface, wherein the second trench structure (3) comprises a second polysilicon structure (41) and a second oxide layer (5) surrounding the second polysilicon structure (41),
wherein the substrate comprises:
a second doped region (13a) located between the first trench structure (3) and the second trench structure (3) and spaced apart from the first trench structure (3) and the second trench structure (3), wherein a distance between the second doped region (13a) and the first trench structure (3) is substantially equal to a distance between the second doped region (13a) and the second trench structure (3).
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 4, in view of NAKANO, the second doped region (13a) extends from the first surface toward the second surface.
With respect to claim 5, in view of NAKANO, the substrate comprises:
a third doped region (15) located between the first surface and the second surface, adjacent to the second oxide layer (5) and separated from the second polysilicon structure (41),
wherein a distance from the first doped region (5) to the first surface is greater than a distance from the second doped region (13a) to the first surface, and a distance from the third doped region (15) to the first surface is greater than the distance from the second doped region (13a) to the first surface.
With respect to claim 6, the second polysilicon structure (30a), comprises a lower portion and an upper portion connected to the lower portion of the second polysilicon structure (39) and extending from the first surface (301) to the lower portion along the first direction,
a width of the upper portion of the second polysilicon structure (39) along the second direction is greater than a width of the lower portion of the second polysilicon structure along the second direction,
the second oxide layer (35) comprises a bottom wall portion below the second polysilicon structure (39), and a sidewall portion (35) surrounding the lower portion of the second polysilicon structure (39),
in view of HERLER, a thickness of the bottom wall portion (630) of the second oxide layer (626) along the first direction is greater than a thickness of the sidewall portion (628) of the second oxide layer (626) along the second direction.
With respect to claim 7, As best understood by the Examiner, in view of HIRLER and NAKANO, the first doped region (636 or 15) has a first lower boundary, the first oxide layer (626 or 5) has a second lower boundary, and the first polysilicon structure (622 or 41) has a third lower boundary.
With respect to claim 8, in view of HIRLER and NAKANO, the first doped region (636 and 15) is located beneath the first trench structure (614 and 3) and is in direct contact with the first oxide layer (626 and 3).
With respect to claim 10, As best understood by the Examiner, in view of HIRLER and NAKANO, the first doped region (636 and 15) has a first lower boundary, the first oxide layer (35) of YEN has a second lower boundary, the lower portion of the first polysilicon structure (39) has a fourth lower boundary, and the upper portion of the first polysilicon structure (39) has a fifth lower boundary.
With respect to claim 11, the substrate of YEN comprises silicon carbide.
With respect to claim 30, in view of NAKANO, a (sic) width of the first doped region (15) is less than a width of the first polysilicon structure (41).
Claims 21-29 are rejected under 35 U.S.C. 103 as being unpatentable over YEN ‘207, in view of NAKANO ‘721 and HIRLER ‘315.
With respect to claim 21, YEN teaches a semiconductor structure substantially as claimed including:
a substrate (30) comprising a first surface (301) and a second surface (302) positioned on an opposite side of the substrate;
a first trench structure (30a, left) extending from the first surface toward the second surface, wherein the first trench structure comprises a first polysilicon structure (39, left) and a first oxide layer (35, left) surrounding the first polysilicon structure (39, left);
a second trench structure (30a, middle) extending from the first surface toward the second surface, wherein the second trench structure comprises a second polysilicon structure (39, middle) and a second oxide layer (35, middle) surrounding the second polysilicon structure;
a shielding metal layer (37) located on the first surface (301) of the substrate and covering the first trench structure (left) and the second trench structure (right);
a first conductive layer (38) disposed on the shielding metal layer (37);
wherein the first oxide layer (35) comprises a bottom wall portion below the first polysilicon structure (39), and a sidewall portion (352) connected to the bottom wall portion and surrounding the first polysilicon structure (39),
a thickness of the bottom wall portion along a first direction and a thickness of the sidewall portion along a second direction substantially orthogonal to the second direction. (See FIG. 3).
Thus, YEN is shown to teach all the features of the claim with the exception of explicitly disclosing a first and second doped regions adjacent to a bottom of the first and second oxide layer; a third doped region located between the first trench structure and the second trench structure; a maximum width of the first doped region being less than a width of the bottom of the first trench structure; and a thickness of the bottom wall portion of the first oxide layer along a first direction is greater than a thickness of the sidewall portion along a second direction substantially orthogonal to the second direction.
However, NAKANO teaches a semiconductor structure including:
a first trench structure (3, left) extending from a first surface (top) of a substrate toward a second surface (bottom), wherein the first trench structure comprises a first polysilicon structure (41) and a first oxide layer (5) surrounding the first polysilicon structure (41),
a second trench structure (3, right) extending from a first surface (top) of a substrate toward a second surface (bottom), wherein the first trench structure comprises a second polysilicon structure (41) and a second oxide layer (5) surrounding the second polysilicon structure (41),
a first doped region (15, left) in the substrate, wherein the first doped region (15) is adjacent to the bottom of the first oxide layer (5) and separated from the first polysilicon structure (41), and wherein a maximum width of the first doped region (15) is less than a width of a bottom of the first trench structure (3);
a second doped region (15, right) in the substrate, wherein the second doped region (15) is adjacent to a bottom of the second oxide layer (3) and separated from the second polysilicon structure (41); and
a third doped region (13a) located between the first trench structure (3, left) and the second trench structure (3, right) and spaced apart from the first trench structure and the second trench structure, wherein a distance between the third doped region (13a) and the first trench structure is substantially equal to a distance between the third doped region (13a) and the second trench structure,
wherein the first oxide layer (3, left) comprises a bottom wall portion below the first polysilicon structure (41, left), and a sidewall portion connected to the bottom wall portion and surrounding the first polysilicon structure (41, left),
a thickness of the bottom wall portion along a first direction and a thickness of the sidewall portion along a second direction substantially orthogonal to the second direction. (See FIG. 7).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor structure of YEN, having the first, second and third doped regions, and the maximum width of the first doped region being less than the width of the bottom of the first trench structure as taught by NAKANO to suppress an increase in on-resistance.
Further, HIRLER teaches a semiconductor structure including:
a first trench structure (614) extending from a first surface (604) of a substrate toward a second surface (606), wherein the first trench structure comprises a first polysilicon structure (622) and a first oxide layer (626) surrounding the first polysilicon structure (622),
wherein the first oxide layer (626) comprises a bottom wall portion (630) below the first polysilicon structure (622), and a sidewall portion (628) connected to the bottom wall portion (630) and surrounding the first polysilicon structure (622),
a thickness of the bottom wall portion (630) along a first direction is greater than a thickness of the sidewall portion (628) along a second direction substantially orthogonal to the second direction. (See FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first dielectric layer of YEN having the thickness of the bottom wall portion along the first direction being greater than the thickness of the sidewall portion along the second direction as taught by HILER to improve the ability of the first oxide layer to withstand breakdown under high reverse voltage conditions.
With respect to claim 22, the first oxide layer of (35) of YEN includes a (sic) bottom portion and sidewall portions located over the bottom portion, the sidewall portions and the bottom wall portion collectively define a space, and the first polysilicon structure is disposed within the space.
With respect to claim 23, the first trench structure (30a, left) of YEN has an arcuate bottom surface.
With respect to claim 24, the first polysilicon structure (39, left) of YEN is in contact with the shielding metal layer.
With respect to claim 25, a top surface of the second polysilicon structure (39, right) of YEN and a top surface of the second oxide layer (35, right) are coplanar with the first surface (301).
With respect to claim 26, in view of NAKANO, a distance from the first doped region (15, left) to the first surface is substantially equal to a distance from the second doped region (15, right) to the first surface.
With respect to claim 27, the first polysilicon structure (39, left) of YEN comprises a lower portion and a upper portion connected to the lower portion and extending from the first surface (301) to the lower portion along the first direction,
a width of the upper portion along the second direction is greater than a width of the lower portion along the second direction.
With respect to claim 28, in view of NAKANO, the third doped region (13a) is located beneath the shielding metal layer (42) and is in direct contact with the shielding metal layer.
With respect to claim 29, in view of NAKANO, a (sic) width of the first doped region (15, left) is less than or equal to a width of the first polysilicon structure (41).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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