DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I and Species 2, was elected.
Amendment filed January 09, 2026 is acknowledged. Claims 1, 3-5, 9, 21 and 27 have been amended. Claims 1-11 and 21-29 are pending.
Action on merits of the Elected Group I, Species 2, claims 1-11 and 21-29 follows.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2 and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over YEN et al. (2014/0145207) of record, in view of HIRLER (US. Pub. No. 2016/0020315).
With respect to claim 1, YEN teaches a semiconductor structure substantially as claimed including:
a substrate (30) comprising a first surface (301) and a second surface (302) positioned on an opposite side of the substrate;
a first trench structure (30a) extending from the first surface toward the second surface, wherein the first trench structure (30a) comprises a first polysilicon structure (39) and a first oxide layer (35) surrounding the first polysilicon structure (39);
a shielding metal layer (37) located on the first surface (301) of the substrate and covering the first trench structure (30a);
a first conductive layer (38) disposed on the shielding metal layer (37) and entirely isolated from the first oxide layer (35) by the shielding metal layer (37);
a second conductive layer (not shown) disposed on the second surface (302) of the substrate; and
wherein the first polysilicon structure (30a) comprises a lower portion and an upper portion connected to the lower portion and extending from the first surface to the lower portion along a first direction,
a width of the upper portion along a second direction is greater than a width of the lower portion along the second direction,
the first direction is substantially orthogonal to the second direction,
the first oxide layer (35) comprises a bottom wall portion below the first polysilicon structure (39), and a sidewall portion surrounding the lower portion of the first polysilicon structure (39). (See FIG. 3).
Thus, YEN is shown to teach all the features of the claim with the exception of explicitly disclosing a thickness of the bottom wall portion along the first direction is greater than a thickness of the sidewall portion along the second direction.
However, HIRLER teaches a semiconductor structure including:
a first trench structure extending from a first surface (604) of a substrate toward a second surface (606), wherein the first trench structure comprises a first polysilicon structure (622) and a first oxide layer (626) surrounding the first polysilicon structure (622),
wherein the first polysilicon structure (622) comprises a lower portion and an upper portion connected to the lower portion and extending from the first surface (604) to the lower portion along a first direction,
the first oxide layer (626) comprises a bottom wall portion (630) below the first polysilicon structure (622), and a sidewall portion (628) surrounding the lower portion of the first polysilicon structure (622), and
a thickness of the bottom wall portion (630) along the first direction is greater than a thickness of the sidewall portion (628) along the second direction. (See FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first dielectric layer of YEN having the thickness of the bottom wall portion along the first direction being greater than the thickness of the sidewall portion along the second direction as taught by HILER to improve the ability of the first oxide layer to withstand breakdown under high reverse voltage conditions.
With respect to claim 2, a top surface of the first polysilicon structure (39) and a top surface of the first oxide layer (35) of YEN are coplanar with the first surface (301).
With respect to claim 6, in view of HIRLER, the second polysilicon structure (same as first polysilicon structure 622), comprises a lower portion and an upper portion connected to the lower portion of the second polysilicon structure (622) and extending from the first surface (604) to the lower portion along the first direction,
a width of the upper portion of the second polysilicon structure (622) along the second direction is greater than a width of the lower portion of the second polysilicon structure along the second direction,
the second oxide layer (626) comprises a bottom wall portion (630) below the second polysilicon structure (622), and a sidewall portion surrounding the lower portion of the second polysilicon structure,
a thickness of the bottom wall portion (630) of the second oxide layer along the first direction is greater than a thickness of the sidewall portion (628) of the second oxide layer along the second direction.
With respect to claim 7, in view of HIRLER, the substrate comprises a second doped region (636) located between the first surface and the second surface, adjacent to the first oxide layer (626) and separated from the first polysilicon structure (622), and the second doped region (636) has a first lower boundary, the first oxide layer (626) has a second lower boundary, and the first polysilicon structure (622) has a third lower boundary.
With respect to claim 8, in view of HIRLER, the substrate comprises a second doped region (636) located between the first surface and the second surface, adjacent to the first oxide layer (626) and separated from the first polysilicon structure (622), and the second doped region (636) is located beneath the first trench structure (614) and is in direct contact with the first oxide layer (626).
With respect to claim 9, the upper portion and the lower portion of YEN form a stepped structure in a cross-sectional view of the semiconductor structure.
With respect to claim 10, in view of HIRLER, the substrate comprises a second doped region (636) located between the first surface and the second surface, adjacent to the first oxide layer (626) and separated from the first polysilicon structure (622), and the second doped region (636) has a first lower boundary, the first oxide layer (626) has a second lower boundary, the lower portion of the first polysilicon structure (622) has a fourth lower boundary, and the upper portion of the first polysilicon structure (622) has a fifth lower boundary.
With respect to claim 11, the substrate of YEN comprises silicon carbide.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over YEN ‘207 and HIRLER ‘315 as applied to claim 1 above, and further in view of QUDDUS (US. Pub. No. 2019/0288125) of record.
With respect to claim 3, YEN, in view of HIRLER, teaches the semiconductor structure as described in claim 1 above and further includes:
a second trench structure (30a) extending from the first surface (301) toward the second surface (302), wherein the second trench structure comprises a second polysilicon structure (39) and a second oxide layer (35) surrounding the second polysilicon structure (39),
wherein the first trench structure is spaced apart from the second trench structure.
Thus, YEN and HIRLER are shown to teach all the features of the claim with the exception of explicitly disclosing a first doped region located between the first trench structure and the second trench structure.
However, QUDDUS teaches a semiconductor structure including:
a first trench structure (50A) and a second trench structure (50B) extending from first surface (14) toward second surface (16), wherein the second trench structure (50B) comprises a second polysilicon structure (64B) and a second oxide layer (54B) surrounding the second polysilicon structure (64B),
wherein the substrate (20) comprises:
a first doped region (82A2) located between the first trench structure (50A) and the second trench structure (50B) and spaced apart from the first trench structure (50A) and the second trench structure (50B), wherein a distance between the first doped region (82A2) and the first trench structure (50A) is substantially equal to a distance between the first doped region and the second trench structure. (See FIG. 9).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to the semiconductor structure of YEN, in view of HIRLER, including the first doped region located between the first trench structure and the second trench structure as taught by QUDDUS to provide for ESD protection.
With respect to claim 4, in view of QUDDUS, the first doped region (82A2) extends from the first surface (14) toward the second surface (16).
With respect to claim 5, in view of HIRLER, the semiconductor structure comprises:
a second doped region (636) located between the first surface (604) and the second surface (606), adjacent to the first oxide layer (626) and separated from the first polysilicon structure (622); and
a third doped region (636) located between the first surface (604) and the second surface (606), adjacent to the second oxide layer (626) and separated from the second polysilicon structure (622),
wherein a distance from the second doped region (636) to the first surface (604) is greater than a distance from the first doped region (82A2) of QUDDUS, to the first surface (604), and a distance from the third doped region (636) to the first surface (604) is greater than the distance from the first doped region (82A2) of QUDDUS to the first surface (604). (See HIRLER, FIG. 2)
Claims 21-29 are rejected under 35 U.S.C. 103 as being unpatentable over YEDINAK et al. (US. Pub. No. 2012/0037982) of record, in view of QUDDUS ‘122 and HIRLER ‘315.
With respect to claim 21, YEDINAK teaches a semiconductor structure substantially as claimed including:
a substrate comprising a first surface (top) and a second surface (bottom) positioned on an opposite side of the substrate;
a first trench structure (130, left) extending from the first surface toward the second surface, wherein the first trench structure comprises a first polysilicon structure (132) and a first oxide layer (134) surrounding the first polysilicon structure (132);
a second trench structure (130, right) extending from the first surface toward the second surface, wherein the second trench structure comprises a second polysilicon structure (132) and a second oxide layer (134) surrounding the second polysilicon structure (132);
a shielding metal layer (140) located on the first surface of the substrate and covering the first trench structure (130, left) and the second trench structure (130, right);
a first conductive layer (145) disposed on the shielding metal layer (140);
a first doped region (170, left) in the substrate, wherein the first doped region is adjacent to a bottom of the first oxide layer (134) and separated from the first polysilicon structure (132);
a second doped region (170, right) in the substrate, wherein the second doped region is adjacent to a bottom of the second oxide layer (134) and separated from the second polysilicon structure (132),
wherein the first oxide layer (134) comprises a bottom wall portion below the first polysilicon structure (132), and a sidewall portion connected to the bottom wall portion and surrounding the first polysilicon structure. (See FIG. 2).
Thus, YEDINAK is shown to teach all the features of the claim with the exception of explicitly disclosing a third doped region located between the first trench structure and the second trench structure; and a thickness of the bottom wall portion along a first direction is greater than a thickness of the sidewall portion along a second direction substantially orthogonal to the second direction.
However, QUDDUS teaches a semiconductor structure including:
a first trench structure (50A) extending from first surface (14) toward second surface (16), wherein the first trench structure comprises a first polysilicon structure (64A) and a first oxide layer (54At) surrounding the first polysilicon structure;
a second trench structure (50B) extending from the first surface toward the second surface, wherein the second trench structure comprises a second polysilicon structure (64B) and a second oxide layer (54B) surrounding the second polysilicon structure; and
a third doped region (82A2) located between the first trench structure (50A) and the second trench structure (50B) and spaced apart from the first trench structure (50A) and the second trench structure (50B), wherein a distance between the third doped region (82A2) and the first trench structure is substantially equal to a distance between the third doped region and the second trench structure. (See FIG. 26).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor structure of YEDINAK having the third doped region between the first and second trenches as taught by QUDDUS to provide for ESD protection.
Further, HIRLER teaches a semiconductor structure including:
a first trench structure (614) extending from the first surface (604) toward the second surface (606), wherein the first trench structure (614) comprises a first polysilicon structure (622) and a first oxide layer (626) surrounding the first polysilicon structure (622),
wherein the first oxide layer comprises a bottom wall portion (630) below the first polysilicon structure (622), and a sidewall portion (628) connected to the bottom wall portion (630) and surrounding the first polysilicon structure (622),
a thickness of the bottom wall portion (630) along a first direction is greater than a thickness of the sidewall portion (628) along a second direction substantially orthogonal to the second direction. (See FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first oxide layer of YEDINAK having the thickness of the bottom wall portion along the first direction being greater than the thickness of the sidewall portion along the second direction as taught by HIRLER to improve the ability of the first oxide layer to withstand breakdown under high reverse voltage conditions.
With respect to claim 22, the first oxide layer of YEDINAK or QUDDUS or HIRLER includes a bottom portion (sic) and sidewall portions located over the bottom portion, the sidewall portions and the bottom wall portion collectively define a space, and the first polysilicon structure is disposed within the space.
With respect to claim 23, the first trench structure of YEDINAK or HIRLER has an arcuate bottom surface.
With respect to claim 24, the first polysilicon structure of YEDINAK or QUDDUS or HIRLER is in contact with the shielding metal layer.
With respect to claim 25, in view of QUDDUS or HIRLER, a top surface of the second polysilicon structure and a top surface of the second oxide layer are coplanar with the first surface.
With respect to claim 26, a distance from the first doped region (170) to the first surface of YEDINAK is substantially equal to a distance from the second doped region (170) to the first surface.
With respect to claim 27, in view of HIRLER, the first polysilicon structure (622) comprises a lower portion and a upper portion connected to the lower portion and extending from the first surface (604) to the lower portion along the first direction,
a width of the upper portion along the second direction is greater than a width of the lower portion along the second direction.
With respect to claim 28, in view of QUDDUS, the third doped region is located beneath the shielding metal layer (90) and is in direct contact with the shielding metal layer.
With respect to claim 29, a width of the first doped region (160) of YEDINAK is less than or equal to a width of the first polysilicon structure (132).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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