DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 10-11, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seshadri et al. (US 2014/0010032 “Seshadri”) in view of Atallah et al. (US. 2016/0247559 “Atallah”).
Regarding claim 1, Seshadri discloses a system comprising:
a turbo circuit (WL drivers 45D functions as a turbo, i.e. energizing, circuit; fig. 5 para 0044) configured to modify (i.e. discharge) a voltage of a tracking bit line (DBL) (REF_BL; fig. 5, i.e. modify the DBL (REF_BL) by discharging a precharge voltage of the DBL (REF_BL); para 0041) enabling sending (drives sense amplifier enable signal SAE; para 0040) of a sense amplifier enable signal (SAE; fig. 3), wherein the turbo circuit (45D) is configured to control the voltage of the DBL (REF_BL) based upon a turbo signal (ROW_EN; fig. 4) and a voltage (charged voltage; para 0041) of a tracking word line (DWL) (REF_WL; fig. 5).
Seshadri does not expressly disclose at a rate faster than a predetermined frequency rate; and a turbo enabling circuit configured to generate the turbo signal and including a NAND circuit.
Seshadri, in an embodiment, teaches a trimmed timing (para 0049) of the predetermined frequency rate of the SAE (the trimmed timing, i.e. reduced timing, is considered to require less time, and therefore is a rate faster than the predetermined frequency rate; para 0049). Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is modifiable as taught for the purpose of providing layout and construction options to minimize proximity effects on neighboring cells (para 0047, 0053-0054), which may otherwise cause coupling disturb as common and well known in the prior art.
Atallah discloses a turbo enabling circuit (word line driver 508B functions to enable a turbo, i.e. boost, circuit 809; fig. 8) configured to generate the turbo signal (804; fig. 8) and including a NAND circuit (806; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is modifiable as taught by Atallah for the purpose of facilitating data accessing schemes by mitigating read disturb (para 0009, 0064+ of Atallah), which is common and well known in the art to avoid points of failure that could otherwise hinder a complex system.
Regarding claim 5, Seshadri discloses the system, wherein a tracking cell (50C; fig. 3, 5) is configured to pull-down the voltage of the DBL (the voltage of REF_BL pulled down to Vssa; para 0048).
Regarding claim 10, Seshadri discloses a method comprising:
generating (via circuit 43; fig. 3) a sense amplifier enable signal (SAE; fig. 3) based on a voltage (precharge voltage; para 0040-0041) of a tracking bit line (DBL) (REF_BL; fig. 5);
modifying (i.e. discharging; para 0041) the voltage (precharge voltage) of the DBL (REF_BL, i.e. modifying the DBL (REF_BL) by discharging the precharge voltage of the DBL (REF_BL); para 0041) based on a turbo signal (ROW_EN) and a voltage (charged voltage; para 0041) of a tracking word line (DWL) (REF_WL; fig. 5).
Seshadri does not expressly disclose generating the turbo signal, using a NAND circuit, based on a turbo enable input signal.
Atallah discloses generate the turbo signal (804; fig. 8), using a NAND circuit (806; fig. 8), based on a turbo enable input signal (511, 510; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is modifiable as taught by Atallah for the purpose of facilitating data accessing schemes by mitigating read disturb (para 0009, 0064+ of Atallah), which is common and well known in the art to avoid points of failure that could otherwise hinder a complex system.
Regarding claim 11, Seshadri discloses the method of claim 10, further comprising: injecting (i.e. inputting) a turbo signal (ROW_EN; fig. 4) into a turbo circuit (WL drivers 45D functions as a turbo, i.e. energizing, circuit; para 0044) to decrease the voltage of the DBL (the voltage of REF_BL decreased to Vssa; para 0048) and the decreased voltage of the DBL triggers the sense enable signal (SAE) to enable performance of read or write operations (via enabling of sense amplifiers 44; para 0048) of a memory device (38; fig. 3).
Regarding claim 17, Seshadri discloses a memory device comprising:
an inverter circuit (43; fig. 3) configured to generate a sense amplifier enable signal (SAE; fig. 3) based on a voltage (precharge voltage; para 0040-0041) of a tracking bit line (DBL) (REF_BL; fig. 5);
a turbo circuit (WL drivers 45D functions as a turbo, i.e. energizing, circuit; fig. 5 para 0044) configured to control the voltage of the DBL (REF_BL) based on the turbo signal (ROW_EN; fig. 4) and a voltage (charged voltage; para 0041) of a tracking word line (DWL) (REF_WL; fig. 5).
Seshadri does not expressly disclose a turbo enabling circuit configured to generate a turbo signal and including a NAND circuit.
Atallah discloses a turbo enabling circuit (word line driver 508B functions to enable a turbo, i.e. boost, circuit 809; fig. 8) configured to generate the turbo signal (804; fig. 8) and including a NAND circuit (806; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is modifiable as taught by Atallah for the purpose of facilitating data accessing schemes by mitigating read disturb (para 0009, 0064+ of Atallah), which is common and well known in the art to avoid points of failure that could otherwise hinder a complex system.
Claim(s) 2, 9, 12-14, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seshadri et al. (US 2014/0010032 “Seshadri”) in view of Atallah et al. (US. 2016/0247559 “Atallah”), and further in view of Kawasumi (US 2013/0250659).
Regarding claim 2, Seshadri discloses the system of claim 1, wherein: a tracking cell couple between the DWL and the DBL is configured to track or imitate (para 0041) at different locations (locations of read/write cells; para 0041) within an array (40; fig. 3) of a memory device (38; fig. 3); the sense amplifier enable signal (SAE) is generated; and the turbo signal (ROW_EN).
Seshadri, as modified, does not expressly disclose track or imitate read or write operations; when the voltage of the DBL falls below a threshold voltage; decreases the voltage of the DBL voltage.
Kawasumi discloses track or imitate read or write operations (para 0037, 0051); the sense amplifier enable signal (SAE; fig. 4) is generated when the voltage of the DBL (the voltage of RBL) falls below a threshold voltage (the voltage of RBL goes low, i.e. lower than a threshold voltage; para 0029, 0037); and the turbo signal decreases the voltage of the DBL voltage (para 0040).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Kawasumi for the purpose of increasing operating speeds by dynamically providing optimal operating signals which better reflect current memory system operating conditions, which is common and well known in the art to improve the overall integrity of a storage system and reduces power consumption (para 0052-0054 of Kawasumi).
Regarding claim 9, Seshadri, as modified, does not expressly disclose the system of claim 1, further comprising a timer transistor gated by the voltage of the tracking word line and the timer transistor is coupled to the turbo circuit.
Kawasumi discloses further comprising a timer transistor (Q5/Q6 functions as a timer transistor by enabling access during a certain time; para 0087) gated (i.e. at a gate terminal) by the voltage of the tracking word line (RWL; para 0037) and the timer transistor is coupled to the turbo circuit (i.e. electrically coupled via RBL; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Kawasumi for the purpose of increasing operating speeds by dynamically providing optimal operating signals which better reflect current memory system operating conditions, which is common and well known in the art to improve the overall integrity of a storage system and reduces power consumption (para 0052-0054 of Kawasumi).
Regarding claim 12, Seshadri, as modified, does not expressly disclose the method of claim 10, wherein a timer transistor gated by the voltage of the tracking word line, and the timer transistor is coupled to a turbo circuit.
Kawasumi discloses a timer transistor (Q5/Q6 functions as a timer transistor by enabling access during a certain time; para 0087) gated (i.e. at a gate terminal) by the voltage of the tracking word line (RWL; para 0037) and the timer transistor is coupled to a turbo circuit (i.e. electrically coupled via RBL; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Kawasumi for the purpose of increasing operating speeds by dynamically providing optimal operating signals which better reflect current memory system operating conditions, which is common and well known in the art to improve the overall integrity of a storage system and reduces power consumption (para 0052-0054 of Kawasumi).
Regarding claim 13, Seshadri discloses the method of claim 10, further comprising: injecting (i.e. inputting) the turbo signal (ROW_EN; fig. 4) into a turbo circuit (WL drivers 45D functions as a turbo, i.e. energizing, circuit; para 0044), wherein the turbo circuit (45D) modifies the voltage of the DBL by pulling down the voltage of the DBL (the voltage of REF_BL decreased to Vssa; para 0048).
Seshadri, as modified, does not expressly disclose using at least two transistors coupled together in series.
Kawasumi discloses wherein the turbo circuit (PRC, further detail having the same configuration as MC; fig. 2, para 0025) modifies the voltage of the DBL by pulling down the voltage of the DBL (para 0037-0040) using at least two transistors coupled together in series (para 0032).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Kawasumi for the purpose of increasing operating speeds by dynamically providing optimal operating signals which better reflect current memory system operating conditions, which is common and well known in the art to improve the overall integrity of a storage system and reduces power consumption (para 0052-0054 of Kawasumi).
Regarding claim 14, Seshadri discloses the method of claim 10, wherein the turbo circuit (50C) modifies the voltage of the DBL (the voltage of REF_BL decreased to Vssa; para 0048).
Seshadri, as modified, does not expressly disclose when the voltage of the DWL and the turbo signal are a logic high.
Kawasumi discloses wherein the turbo circuit modifies the voltage of the DBL when the voltage of the DWL (RWL) and the turbo signal are a logic high (i.e. assertion of RWL and the binary signal(s); para 0037, 0040-0043).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Kawasumi for the purpose of increasing operating speeds by dynamically providing optimal operating signals which better reflect current memory system operating conditions, which is common and well known in the art to improve the overall integrity of a storage system and reduces power consumption (para 0052-0054 of Kawasumi).
Regarding claim 19, Seshadri, as modified, does not expressly disclose the memory device of claim 17, further comprising a timer transistor gated by the voltage of the tracking word line and the timer transistor is coupled to the turbo circuit.
Kawasumi discloses a timer transistor (Q5/Q6 functions as a timer transistor by enabling access during a certain time; para 0087) gated (i.e. at a gate terminal) by the voltage of the tracking word line (RWL; para 0037) and the timer transistor is coupled to the turbo circuit (i.e. electrically coupled via RBL; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Kawasumi for the purpose of increasing operating speeds by dynamically providing optimal operating signals which better reflect current memory system operating conditions, which is common and well known in the art to improve the overall integrity of a storage system and reduces power consumption (para 0052-0054 of Kawasumi).
Claim(s) 3-4, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seshadri et al. (US 2014/0010032 “Seshadri”) in view of Atallah et al. (US. 2016/0247559 “Atallah”), and further in view of Funane et al. (US 2011/0032751 “Funane”).
Regarding claim 3, Seshadri, as modified, does not expressly disclose the system of claim 1, wherein the turbo circuit includes a transistor having a gate terminal configured to receive the turbo signal and a source/drain terminal coupled to the DBL.
Funane teaches the turbo circuit (Ac1_a and DR1; fig. 5) includes a transistor (Ac1_a) having a gate terminal coupled to the turbo signal (TRMAh; fig. 5) and a source/drain terminal coupled to the DBL (RBLA; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Funane for the purpose of increasing a discharge of the tracking bit line (para 0061 of Funane), which facilitates operation speeds during data accessing schemes.
Regarding claim 4, Seshadri, as modified, does not expressly disclose the system of claim 1, wherein the turbo circuit includes a logic gate having a first input terminal configured to receive the turbo signal and a second input terminal coupled to the DBL.
Funane teaches the turbo circuit (Ac1_a and DR1; fig. 5) includes a logic gate (Ac1_a) having a first input terminal (i.e. gate terminal) configured to receive the turbo signal (TRMAh; fig. 5) and a second input terminal (i.e. source/drain terminal) coupled to the DBL (RBLA; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Funane for the purpose of increasing a discharge of the tracking bit line (para 0061 of Funane), which facilitates operation speeds during data accessing schemes.
Regarding claim 18, Seshadri, as modified, does not expressly disclose the memory device, wherein the turbo circuit comprises: a first transistor having a gate terminal coupled to the turbo signal and a source/drain terminal coupled to the DBL; and a second transistor having a gate terminal coupled to the DWL and a source/drain terminal coupled to another source/drain terminal of the first transistor.
Funane teaches the turbo circuit (Ac1_a and DR1; fig. 5) comprises: a first transistor (Ac1_a) having a gate terminal coupled to the turbo signal (TRMAh; fig. 5) and a source/drain terminal coupled to the DBL (RBLA; fig. 5); and a second transistor (Dr_1) having a gate terminal coupled to the DWL (RWLA; fig. 5) and a source/drain terminal coupled to another source/drain terminal of the first transistor (Ac1_a).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Funane for the purpose of increasing a discharge of the tracking bit line (para 0061 of Funane), which facilitates operation speeds during data accessing schemes.
Claim(s) 6-7, 15-16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seshadri et al. (US 2014/0010032 ‒hereinafter Seshadri) in view of Atallah et al. (US. 2016/0247559 “Atallah”), and further in view of Chun et al. (US 2005/0035796 ‒hereinafter Chun).
Regarding claim 6, Seshadri discloses the system, further comprising: a supply voltage (Vdda/Vssa; fig. 5); configured to generate the turbo signal (ROW_EN).
Seshadri, as modified, does not expressly disclose a voltage detector circuit configured to detect a voltage difference between a supply voltage and a reference voltage; and a dual inverter circuit coupled to the voltage detector circuit configured to generate the signal based on the voltage difference.
Chun discloses a voltage detector circuit (120; fig. 3) that detects a voltage difference between a supply voltage VCC and a reference voltage VREF (para 0027); and a dual inverter circuit (INV12, INV14; fig. 4) coupled to the voltage detector circuit configured to generate the signal (PVCCDET; fig. 4) based on the voltage difference.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Chun for the purpose of detecting the power supply voltage with a known detection circuit and link the turbo signal in order to have variable timing based on the power supply voltage (para 0011 of Chun).
Regarding claim 7, Seshadri discloses the system, further comprising: configured to provide the turbo signal (ROW_EN).
Seshadri, as modified, does not expressly disclose an inverter circuit electrically coupled to the dual inverter circuit and configured to generate a handshake signal; and a logic gate configured to provide the signal to a clock generator based upon the handshake signal.
Chun discloses an inverter circuit (INV16, INV18, INV20; fig. 5) electrically coupled to the dual inverter circuit (INV12, INV14; fig. 4) and configured to generate a handshake signal (PVCCHENB; fig. 5); and a logic gate (G10; fig. 6) configured to provide the signal (PVCCDET; fig. 3) to a clock generator (150; fig. 3) based upon the handshake signal (PVCCHENB; fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Chun for the purpose of generating the handshake signal with known practices in the prior art and link the turbo signal in order to properly provide signal transmission between devices (para 0012 of Chun).
Regarding claim 15, Seshadri discloses the method of claim 10, further comprising: a supply voltage (Vdda/Vssa; fig. 5); and generating the turbo signal (ROW_EN).
Seshadri, as modified, does not expressly disclose detecting, using a voltage detector circuit, a voltage difference between a supply voltage and a reference voltage; and generating, using a dual inverter circuit coupled to the voltage detector circuit, the signal when the supply voltage exceeds the reference voltage.
Chun discloses detecting, using a voltage detector circuit (120; fig. 3), a voltage difference between a supply voltage and a reference voltage (para 0027); and generating, using a dual inverter circuit (INV12, INV14; fig. 4) coupled to the voltage detector circuit, the signal (PVCCDET; fig. 4) when the supply voltage exceeds the reference voltage (para 0027).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Chun for the purpose of detecting the power supply voltage with a known detection circuit and link the turbo signal in order to have variable timing based on the power supply voltage (para 0011 of Chun).
Regarding claim 16, Seshadri discloses the method of claim 10, further comprising: a supply voltage (Vdda/Vssa; fig. 5); and generating the turbo signal (ROW_EN).
Seshadri, as modified, does not expressly disclose detecting, using a voltage detector circuit, a voltage difference between a supply voltage and a reference voltage; and generating, using the NAND circuit, based on the supply voltage exceeding the reference voltage and the turbo enable input signal.
Atallah discloses generating the turbo signal (804; fig. 8), using the NAND circuit (806; fig. 8), based on the turbo enable input signal (511, 510; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is modifiable as taught by Atallah for the purpose of facilitating data accessing schemes by mitigating read disturb (para 0009, 0064+ of Atallah), which is common and well known in the art to avoid points of failure that could otherwise hinder a complex system.
Chun discloses disclose detecting, using a voltage detector circuit(120; fig. 3), a voltage difference between a supply voltage and a reference voltage (para 0027), based on the supply voltage exceeding the reference voltage (para 0027).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Chun for the purpose of detecting the power supply voltage with a known detection circuit and link the turbo signal in order to have variable timing based on the power supply voltage (para 0011 of Chun).
Regarding claim 20, Seshadri, discloses the memory device of claim 17, wherein the turbo signal is generated (ROW_EN).
Seshadri, as modified, does not expressly disclose generated based on an applied voltage to the inverter circuit exceeding a predetermined reference voltage.
Chun discloses the signal (PVCCDET; fig. 4) is generated based on an applied voltage to the inverter circuit (INV12, INV14; fig. 4) exceeding a predetermined reference voltage (para 0027).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Seshadri is further modifiable as taught by Chun for the purpose of detecting the power supply voltage with a known detection circuit and link the turbo signal in order to have variable timing based on the power supply voltage (para 0011 of Chun).
Allowable Subject Matter
Claim(s) 8 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 8, the prior art fails to teach or suggest the claimed limitations, namely an inverter circuit coupled to an output of the NAND circuit, the inverter circuit being configured to generate the turbo signal based on the voltage difference and the turbo enable input signal.
The allowable claims are supported in at least fig. 6 of the instant application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 12,183,429. Although the claims at issue are not identical, they are not patentably distinct from each other because the only differences are nominal and would have been obvious to one of ordinary skill in the art.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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