DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cho (US Pat Pub 2012/0099390).
Regarding claims 1, 12 and 19, Cho discloses a memory circuit (for example figs. 1 – 6 and all related texts), comprising:
a first memory bank including a first memory array (310A, fig. 3, or 510A, fig. 5, for example);
a first local input/output (I/O) circuit operatively coupled to the first memory bank (for example, NT1/NT2 gating the local I/O lines LIO1/LIOB1, fig. 3, or referred to in fig. 5 as I/OSA1 connected to LIO1/LIOB1 in fig. 5);
a second memory bank including a second memory array (310B, fig. 3, or 510B, fig. 5);
a second local I/O circuit operatively coupled to the second memory bank (referred to as the circuit 320B of fig. 3, or 520B of fig. 5);
a global I/O circuit (referred to in fig. 3 as circuit 340, or in fig. 5 as 560) operatively coupled between the first local I/O circuit (330A of fig. 3 or 530A of fig. 5) and the second local I/O circuit (330B of fig. 3 or 530B of fig. 5), wherein the global I/O circuit (340 of fig. 3 or 560 of fig. 5) is configured to latch a data bit read from the first memory array (310A, fig. 3 or 510A, fig. 5) through the first local I/O circuit or read from the second memory array through the second local I/O circuit (as shown in fig. 3 or 5. See also para 0006, 0007, or texts of claim 9);
a first local latch circuit operatively coupled to the first local I/O circuit (referred to as the circuit 320A of fig. 3 or 520A of fig. 5), wherein the first local latch circuit is configured to be activated to latch the data bit when read from the first memory array (inherently 320 is to latch data bit read from 310A, fig. 3; or 520 is to latch data bit read from 510A, fig. 5);
a second local latch circuit operatively coupled to the second local I/O circuit, wherein the second local latch circuit is configured to be activated to latch the data bit when read from the second memory array (circuit 320B to latch or buffer data bit from second array 310B; or in fig. 5, circuit 520B to latch/buffer data bit from second array 510B);
wherein the first local latch circuit and the second local latch circuit are configured to be alternately activated (see para 0046, 0058, 0073, and texts of claims 7, 10 and 15).
Regarding claims 2 and 13, Cho also discloses the memory circuit of claim 1, wherein the first local I/O circuit is coupled to the first memory array through a pair of first bit lines (referred to as bit line pair LIO1/LIOB1, fig. 3, or in fig. 5 as bit line pair LIO1/LIOB1), and the second local I/O circuit is coupled to the second memory array through a pair of second bit lines (referred to for example in fig. 3 as LIO2/LIOB2, or in fig. 5 as pair LIO2/LIOB2).
Regarding claims 3 and 20, Cho also discloses the memory circuit of claim 2, wherein the first local I/O circuit includes a first sense amplifier (referred to in fig. 5, for example, as sense amp 540A) selectively activated by a first enable signal (IOSTRB1, fig. 5), and the second local I/O circuit includes a second sense amplifier (540B, fig. 5) selectively activated by a second enable signal (IOSTRB2, fig. 5).
Regarding claims 4 and 14, Cho also discloses the memory circuit of claim 3, wherein when the first sense amplifier is activated (for example sense amp 540A of fig. 5 is activated), one of the pair of first bit lines (LIO1/LIOB1, fig. 5) rises and the other of the pair of first bit lines (LIO2/LIOB2) falls, causing the data bit to be locally latched by the first local latch circuit (as shown in fig. 6, the timing of tSEN of LIO1/LIOB1 activates data latch D0 and after that is complete, tSEN activates D1 of second amplifier at a later time, alternately. Fig. 4 also illustrates similar operation behavior as D0 and D1 alternately latching data from first memory array and second memory array, respectively).
Regarding claims 5 and 15, Cho also discloses the memory circuit of claim 4, wherein the first local latch circuit is activated prior to the first sense amplifier being activated (inherently, the page buffer responsible for the activated local bit line pair within the memory array has to latch/buffer the output bit before the data bit is seen from the corresponding sense amplifier, as can be seen in fig. 5).
Regarding claims 6 and 16, Cho also discloses the memory circuit of claim 5, wherein the first local latch circuit is activated in response to the first memory bank being selected (for example in the embodiment of fig. 5, the circuit 520A must inherently be activated in response to the memory bank 510A being activated. And similarly for latch/buffer circuit 520B for the memory array 510B).
Regarding claims 7 and 17, Cho also discloses the memory circuit of claim 3, wherein when the second sense amplifier is activated, one of the pair of second bit lines rises and the other of the pair of second bit lines falls, causing the data bit to be locally latched by the second local latch circuit (see similar ground for the rejection of claim 4 above with corresponding circuit components).
Regarding claims 8 and 18, Cho also discloses the memory circuit of claim 7, wherein the second local latch circuit is activated prior to the second sense amplifier being activated (see similar ground for the rejection of claim 5 above with corresponding circuit components).
Regarding claim 9, Cho also discloses the memory circuit of claim 8, wherein the second local latch circuit is activated in response to the second memory bank being selected (see similar ground for the rejection of claim 6 above with corresponding circuit components).
Regarding claim 10, Cho also discloses the memory circuit of claim 1, wherein the first memory bank (referred to as the memory array in fig. 3 or 5) includes a plurality of the first memory arrays (which are referred to as the memory blocks in para 0017), and the second memory bank (second memory array in fig. 3 or 4) includes a plurality of the second memory arrays (as “number of cell blocks” in para 0017).
Regarding claim 11, Cho also discloses the memory circuit of claim 10, wherein the global I/O circuit is physically disposed between the first memory bank and the second memory bank along a lateral direction, with the first local I/O circuit interposed between adjacent ones of the first memory arrays along the lateral direction and with the second local I/O circuit interposed between adjacent ones of the second memory arrays along the lateral direction (this is considered to be circuit layout/placement/disposition/arrangement, which can be seen in para 0051 and texts of claim 8, 16, 20, 21).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 June 4, 2026
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