Prosecution Insights
Last updated: October 01, 2026
Application No. 18/962,220

METHOD FOR INSPECTING PATTERN DEFECTS

Non-Final OA §DP
Filed
Nov 27, 2024
Priority
Feb 27, 2020 — provisional 62/982,722 +1 more
Examiner
TON, TRI T
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1032 granted / 1199 resolved
+26.1% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
32 currently pending
Career history
1230
Total Applications
across all art units

Statute-Specific Performance

§101
4.4%
-35.6% vs TC avg
§103
52.0%
+12.0% vs TC avg
§102
21.8%
-18.2% vs TC avg
§112
15.1%
-24.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1199 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions 1. Applicant’s election of Group I, Claims 1-16 in the reply filed on 08/24/26 is acknowledged. Claims 17-20 were canceled. 2. New added claims 21-24 are restricted with Restriction to one of the following inventions is required under 35 U.S.C. 121: 3. Group I: claims 1-16: drawn to a method for inspecting pattern defects comprising searching one or more of the plurality of patterns, show an intensity of the secondary electrons different from others of the plurality of patterns, comparing the intensity of the secondary electrons of the plurality of patterns, scanning only the part of the plurality of patterns with an electron beam is performed in a skipped manner, during the scanning the part of the first group of the plurality of patterns, the electron beam does not scan the defect, the plurality of patterns comprise line-and-space patterns having a plurality of line patterns disposed spaced apart from each other, and the plurality of line patterns are more conductive than the underlying layer (Applicant Pub. No. 2025/0093278, Figures 3A-B). 4. Group II: new added claims 21-24: drawn to a test device for detecting a defect comprising forming a resist pattern over the conductive layer, the resist pattern defining a process control module (PCM) comprising a first inspection pattern and a second inspection pattern; and etching the conductive layer using the resist pattern as an etching mask to form a plurality of convex line patterns of the first inspection pattern and the plurality of convex line patterns of the second inspection pattern over the underlying insulating layer, wherein: the plurality of convex line patterns in the first inspection pattern and the second inspection pattern are electrically isolated from each other; and at least one of a line pitch or a line width of the plurality of convex line patterns of the first inspection pattern is different from that of the plurality of convex line patterns of the second inspection pattern, (Applicant Pub. No. 2025/0093278, Figures 1A, 8). 5. The inventions are distinct, each from the other because of the following reasons: Inventions I, II, are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct from each other if they are shown to be separately usable. 6. Because Applicant had elected Group I for examining, Group II (new added claims 21-24) is withdrawn. The requirement is still deemed proper and is therefore made FINAL. Information Disclosure Statement 7. The information disclosure statement (IDS) submitted on 11/27/24 has been entered. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings 8. The drawings filed on 11/27/24. These drawings are acceptable. Double Patenting 9. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 10. Claims 1-16 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of Chen et al. (U.S. Patent No. 12,196,687). Hereafter, “Chen ‘687”. As to claim 1, Chen ‘687 claims: a method for inspecting pattern defects, the method comprising: forming a plurality of patterns over an underlying layer, the plurality of patterns being electrically isolated from each other (claim 1, lines 3-7); charging the plurality of patterns by scanning only a part of the plurality of patterns with an electron beam (claim 1, lines 8-10); obtaining an intensity of secondary electrons emitted from the scanned part of the plurality of patterns (claim 1, lines 11-12); and searching one or more of the plurality of patterns only the part of which are scanned and which show an intensity of the secondary electrons different from others of the plurality of patterns only the part of which are scanned, (claim 1, lines 12-16), by comparing the intensity of the secondary electrons of the plurality of patterns with each other to obtain a location of a defect, (claim 1, lines 16-19), wherein: during the scanning the part of the plurality of patterns, the electron beam does not scan the defect, the plurality of patterns comprise line-and-space patterns having a plurality of line patterns disposed spaced apart from each other, (claim 1, lines 20-24), wherein the plurality of line patterns are more conductive than the underlying layer, (claim 3) scanning only the part of the plurality of patterns with an electron beam is performed in a skipped manner (claim 1, lines 29-30), and the skipped manner includes performing an odd line-pattern scanning and performing an even line-pattern scanning, wherein the odd line-pattern scanning and the even line-pattern scanning are performed along a same path within the part of the plurality of patterns, (claim 1, lines 31-35). As to claim 2, Chen ‘687 claims wherein the plurality of line patterns are conductive and the underlying layer is insulative, (claim 2). As to claim 3, Chen ‘687 claims forming a frame pattern surrounding the plurality of patterns over the underlying layer, (claim 8, lines 3-5). As to claim 4, Chen ‘687 claims wherein the plurality of patterns are electrically isolated from the frame pattern (claim 8, lines 5-7). As to claim 5, Chen ‘687 claims plurality of patterns comprises a defect that is a broken line pattern (claim 4). As to claim 6, Chen ‘687 claims the plurality of patterns comprises a defect that is a bridge of adjacent line patterns (claim 5). As to claim 7, Chen ‘687 claims when an entire length of each of the plurality of line patterns is Al, and a length A2 of the part of the plurality of patterns along a direction in which the plurality of line patterns extend, A2 is in a range from 1% to 20% of Al (claim 1, lines 25-28). As to claim 8, Chen ‘687 claims when one of the plurality of patterns showing the intensity of the secondary electrons different from others of the plurality of patterns is found, obtaining the location of the one of the plurality of patterns (claim 6). As to claim 9, Chen ‘687 claims observing the one of the plurality of patterns of which location is obtained along a direction in which the plurality of line patterns extend to find a defect (claim 7). As to claim 10, Chen ‘687 claims a method for inspecting pattern defects, the method comprising: forming groups of a plurality of patterns over an underlying layer, the plurality of patterns being electrically isolated from each other (claim 8, lines 3-7); charging the plurality of patterns by scanning only a part of a first group of the plurality of patterns with an electron beam to find a defect (claim 8, lines 8-10); obtaining an intensity of secondary electrons emitted from the scanned part of the first group of the plurality of patterns (claim 8, lines 11-13); searching one or more of the plurality of patterns in the first group only the part of which are scanned and which show an intensity of the secondary electrons different from others of the plurality of patterns only the part of which are scanned in the first group (claim 8, lines 14-18), by comparing the intensity of the secondary electrons of the first group of the plurality of patterns with each other (claim 8, lines 18-20); when one of the plurality of patterns showing the intensity of the secondary electrons different from others of the plurality of patterns is found, obtaining a location of the one of the plurality of patterns (claim 8, lines 21-24); and scanning a part of a second group of the plurality of pattern with the electron beam to find a defect (claim 8, lines 25-26), wherein: during the scanning the part of the first group of the plurality of patterns, the electron beam does not scan the defect, the plurality of patterns comprise line-and-space patterns having a plurality of line patterns disposed spaced apart from each other (claim 8, lines 27-31), and the plurality of line patterns are more conductive than the underlying layer (claim 3), scanning only the part of the first group of the plurality of patterns with an electron beam is performed in a skipped manner (claim 8, lines 36-38), and the skipped manner includes performing an odd line-pattern scanning and performing an even line-pattern scanning, wherein the odd line-pattern scanning and the even line-pattern scanning are performed along a same path within the part of the first group of the plurality of patterns (claim 8, lines 39-44). As to claim 11, Chen ‘687 claims the plurality of line patterns are conductive, and the underlying layer is insulative (claim 2). As to claim 12, Chen ‘687 claims wherein the plurality of patterns in each of the groups comprise line-and-space patterns having a plurality of line patterns disposed spaced apart from each other (claim 1, lines 22-24). As to claim 13, Chen ‘687 claims wherein at least one of a pattern width, a pattern pitch or a pattern direction of the plurality of line patterns in the first group is different from that in the second group (claim 11). As to claim 14, Chen ‘687 claims wherein the underlying layer is disposed over a semiconductor wafer, and the semiconductor wafer is a test wafer on which no pattern that is or is to be a part of a transistor is formed (claim 12). As to claim 15, Chen ‘687 claims when an entire length of each of the plurality of line patterns is A1, and a length A2 of the part of the plurality of patterns along a direction in which the plurality of line patterns extend, A2 is in a range from 1% to 20% of A1 (claim 8, lines 32-35). As to claim 16, Chen ‘687 claims wherein A2 is in a range from 1% to 10% of A1 (claim 14). Allowable Subject Matter 11. Claim 1-16 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting, set forth in this Office action. 12. The following is a statement of reasons for the indication of allowable subject matter: there was no prior art found by the examiner that suggested modification or combination with the cited art so as to satisfy the combination of all the limitations in claims 1, and 10. 13. As claim 1, the prior art of record taken alone or in combination, fails to disclose or render obvious a method for inspecting pattern defects comprising forming a plurality of patterns over an underlying layer, the plurality of patterns being electrically isolated from each other; charging the plurality of patterns; obtaining an intensity of secondary electrons emitted from the scanned part of the plurality of patterns; and comparing the intensity of the secondary electrons of the plurality of patterns with each other to obtain a location of a defect, wherein: during the scanning the part of the plurality of patterns, the electron beam does not scan the defect, the plurality of patterns comprise line-and-space patterns having a plurality of line patterns disposed spaced apart from each other, wherein the plurality of line patterns are more conductive than the underlying layer, performing an odd line-pattern scanning and performing an even line-pattern scanning, wherein the odd line-pattern scanning and the even line-pattern scanning are performed along a same path within the part of the plurality of patterns; in combination with the rest of the limitations of claim 1. 14. As claim 10, the prior art of record taken alone or in combination, fails to disclose or render obvious a method for inspecting pattern defects comprising: forming groups of a plurality of patterns over an underlying layer, the plurality of patterns being electrically isolated from each other; charging the plurality of patterns; obtaining an intensity of secondary electrons emitted from the scanned part of the first group of the plurality of patterns; comparing the intensity of the secondary electrons of the first group of the plurality of patterns with each other; when the intensity of the secondary electrons different from others of the plurality of patterns is found, obtaining a location of the one of the plurality of patterns; wherein: during the scanning the part of the first group of the plurality of patterns, the electron beam does not scan the defect, the plurality of patterns comprise line-and-space patterns having a plurality of line patterns disposed spaced apart from each other, and the plurality of line patterns are more conductive than the underlying layer, scanning skipped manner includes performing an odd line-pattern scanning and performing an even line-pattern scanning, wherein the odd line-pattern scanning and the even line-pattern scanning are performed along a same path within the part of the first group of the plurality of patterns; in combination with the rest of the limitations of claim 10. Fax/Telephone Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRI T TON whose telephone number is (571)272-9064. The examiner can normally be reached on 8am-4pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michelle Iacoletti can be reached on (571)270-5789. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. September 19, 2026 /Tri T Ton/ Primary Examiner Art Unit 2877
Read full office action

Prosecution Timeline

Nov 27, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
97%
With Interview (+10.5%)
2y 1m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1199 resolved cases by this examiner. Grant probability derived from career allowance rate.

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