DETAILED ACTION
The action is responsive to the following communications: the Application filed December 03, 2024 and the information disclosure statement (IDS) filed September 25, 2025. This application is a CON of 17/234,160.
Claims 1-20 are pending. Claims 1, 8 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 25, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,190,944. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,190,944
Comment
Claim 1. A memory device, comprising:
row driver circuitry; and
a memory array operably connected to the row driver circuitry and comprising: a plurality of memory cells arranged in rows and columns;
a word line operably connected to the memory cells in each row, wherein a proximate end of each word line is operably connected to the row driver circuitry;
a delay circuit configured to receive a clock signal and to output a delayed clock signal; and
signal edge sharpener circuitry operably connected to a distal end of each word line and to the delay circuit, the signal edge sharpener circuitry configured to pull up a rising edge of a word line signal on the word line at an increased rate in response to the delayed clock signal.
Claim 13. A system, comprising:
a processing device; and
a memory device operably connected to the processing
device, the memory device comprising:
a memory cell;
a word line operably connected to the memory cell, wherein a proximate end of the word line is operably connected to row driver circuitry;
a delay circuit configured to receive a clock signal and
output a delayed clock signal;
signal edge sharpener circuitry operably connected between a distal end of the word line and an output of the delay circuit, the signal edge sharpener circuitry
having a control terminal configured to receive the delayed clock signal and responsively pull up a rising edge of a word line signal on the word line at
an increased rate; and
a load circuit operably connected to the output of the delay circuit.
Note footnote1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar et al. (US 2019/0221256).
Regarding independent claim 8, Kumar et al. disclose a memory device, comprising:
row driver circuitry (FIG. 2A: 130A); and
a memory array (110-0,9 – 110-9,11) operably connected to the row driver circuitry (see FIG. 2A) and comprising:
a plurality of memory cells arranged in rows and columns (FIG. 2A);
a word line operably connected to the memory cells in each row, wherein a proximate end of each word line is operably connected to the row driver circuitry (FIG. 2A); and
signal edge sharpener circuitry (FIG. 2A: 160A and FIG. 2B) operably connected to a distal end of each word line (see FIGS. 2A-B).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7 and 9-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2019/0221256) in view of Bindra et al. (US 2018/0108388).
Regarding independent claim 1, Kumar et al. teach a memory device, comprising:
row driver circuitry (FIG. 2A: 130A); and
a memory array operably connected to the row driver circuitry (see FIG. 2A) and comprising:
a plurality of memory cells (110-0,9 – 110-9,11) arranged in rows and columns; a word line operably connected to the memory cells in each row, wherein a proximate end of each word line is operably connected to the row driver circuitry (see FIG. 2A); and
signal edge sharpener circuitry (FIG. 2A: 160A and FIG. 2B) operably connected to a distal end of each word line and to the delay circuit (see FIG. 2A), the signal edge sharpener circuitry configured to pull up a rising edge of a word line signal on the word line at an increased rate in response to the delayed clock signal (see FIG. 2A-B, and accompanying disclosure).
Kumar et al.’s clock signal (FIGS 2A-B: RA_CLK) does not explicitly disclose a delay circuit configured to receive a clock signal and to output a delayed clock signal.
Bindra et al. teach the deficiencies in e.g., FIG. 2A and accompanying disclosure, e.g., para. 0020, i.e., a delayed buffer may be used an electronic circuit such as logic circuit to assist (i.e., Kumar’s assist circuitry) a delayed path for a clock or data signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bindra et al. to the teaching of Kumar et al. such that a memory, as taught by Kumar et al., utilizes a delay circuit, as taught by Bindra et al., for the purpose of utilizing synchronous logic circuit in a memory device, thereby enhancing memory operations.
Regarding claim 2, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach the signal edge sharpener circuitry comprises a p-type transistor (FIG. 2B).
Regarding claim 4, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach the row driver circuitry comprises a first row driver circuitry; and the signal edge sharpener circuitry comprises second row driver circuitry (FIG. 2A).
Regarding claim 5, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach the memory device is a static random access memory device (FIG. 1).
Regarding claim 6, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 1.
Kumar et al. and Bindra et al. do not explicitly disclose a load circuit operably connected to an output of the delay circuit.
However, a load circuit connected to an output of the delay circuit is a well-known technology for a type of static random access memory for its purpose.
For support, of the above asserted facts, see for example, Lu et al. (US 2013/0051128), e.g., FIG. 1 and para. 0005: … load devices may include … capacitance ...
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a load circuit to a delay circuit because these conventional technology are well established in the art of the memory devices.
Regarding claim 7, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 6.
Kumar et al. and Bindra et al. do not explicitly disclose the load circuit comprises a p-type transistor, the gate of the p-type transistor operably connected to the output of the delay circuit.
However, as cited in claim 6, Lu’s capacitance as a load circuit is a semiconductor device. In a semiconductor memory device, capacitance comprising C-MOS device is a well-known technology for a type of static random access memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize MOS-CAP in a semiconductor device because these conventional technology are well established in the art of the memory devices.
Regarding claim 9, Kumar et al. teach the limitations of claim 8.
Kumar et al. further teach the signal edge sharpener circuitry is configured to pull up a rising edge of a word line signal on the word line at an increased rate in response to receiving a delayed clock signal (FIGS. 2A-B and accompanying disclosure).
Kumar et al.’s clock signal (FIGS 2A-B: RA_CLK) does not explicitly disclose a delay clock signal.
Bindra et al. teach the deficiencies in e.g., FIG. 2A and accompanying disclosure, e.g., para. 0020, i.e., a delayed buffer may be used an electronic circuit such as logic circuit to assist (i.e., Kumar’s assist circuitry) a delayed path for a clock or data signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bindra et al. to the teaching of Kumar et al. such that a memory, as taught by Kumar et al., utilizes a delay circuit, as taught by Bindra et al., for the purpose of utilizing synchronous logic circuit in a memory device, thereby enhancing memory operations.
Regarding claim 10, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 9.
Kumar et al. further teach the signal edge sharpener circuitry comprises a p-type transistor (FIG. 2B).
Regarding claim 11, Kumar et al. teach the limitations of claim 8.
Kumar et al. further teach the signal edge sharpener circuitry is configured to pull down a falling edge of a word line signal on the word line at an increased rate in response to receiving a delayed clock signal (FIGS. 2A-B).
Kumar et al.’s clock signal (FIGS 2A-B: RA_CLK) does not explicitly disclose a delay clock signal.
Bindra et al. teach the deficiencies in e.g., FIG. 2A and accompanying disclosure, e.g., para. 0020, i.e., a delayed buffer may be used an electronic circuit such as logic circuit to assist (i.e., Kumar’s assist circuitry) a delayed path for a clock or data signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bindra et al. to the teaching of Kumar et al. such that a memory, as taught by Kumar et al., utilizes a delay circuit, as taught by Bindra et al., for the purpose of utilizing synchronous logic circuit in a memory device, thereby enhancing memory operations.
Regarding claim 12, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 11.
Kumar et al. and Bindra et al. do not explicitly disclose the signal edge sharpener circuitry comprises a n-type transistor.
However, n-type transistor edge sharpener, instead of Kumar’s p-type transistor sharpener.
For support, of the above asserted facts, see for example, Frederick (US 2007/0159909), FIG. 6: 85 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used a n-type sharpener circuit because these conventional technology are well established in the art of the memory devices.
Regarding claim 13, Kumar et al. teach the limitations of claim 8.
Kumar et al. do not explicitly disclose a delay circuit configured to receive a clock signal and to output a delayed clock signal to the signal edge sharpener circuitry.
Bindra et al. teach the deficiencies in e.g., FIG. 2A and accompanying disclosure, e.g., para. 0020, i.e., a delayed buffer may be used an electronic circuit such as logic circuit to assist (i.e., Kumar’s assist circuitry) a delayed path for a clock or data signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bindra et al. to the teaching of Kumar et al. such that a memory, as taught by Kumar et al., utilizes a delay circuit, as taught by Bindra et al., for the purpose of utilizing synchronous logic circuit in a memory device, thereby enhancing memory operations.
Regarding claim 14, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 13.
Bindra et al. further teach the delay circuit comprises a buffer circuit (see FIG. 2A).
Kumar et al. further teach a circuit operably connected to a gate of a transistor of the signal edge sharpener circuitry (see FIGS. 2A-B).
Regarding claim 15, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 13.
Kumar et al. and Bindra et al. do not explicitly disclose a load circuit operably connected to an output of the delay circuit.
However, a load circuit connected to an output of the delay circuit is a well-known technology for a type of static random access memory for its purpose.
For support, of the above asserted facts, see for example, Lu et al. (US 2013/0051128), e.g., FIG. 1 and para. 0005: … load devices may include … capacitance ...
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a load circuit to a delay circuit because these conventional technology are well established in the art of the memory devices.
Regarding claim 16, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 8.
Kumar et al. further teach the memory device is a static random access memory device (FIG. 1).
Regarding claim 17, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 8.
Kumar et al. further teach the row driver circuitry comprises a first row driver circuitry; and the signal edge sharpener circuitry comprises second row driver circuitry (FIG. 2A).
Regarding claim 18, Kumar et al. and Bindra et al., as combined, teach the limitations of claim 8.
Kumar et al. further teach the memory device connects to a processing device (FIGS. 2A-B).
Regarding independent claim 19 and claim 20, Kumar et al. teach a method, comprising:
receiving, by a delay circuit of a memory array, a clock signal (see FIG. 2A);
transmitting, by the delay circuit, a delayed signal to a signal edge sharpener circuitry of the memory array (FIG. 2A);
based on the delayed signal, causing, by the signal edge sharpener circuitry, a rising edge of a word line signal on a word line to be pulled up or pulled down, the word line operably connected to a plurality of memory cells of the memory array (FIGS. 2A-B, and accompanying disclosure).
Kumar et al.’s clock signal (FIGS 2A-B: RA_CLK) does not explicitly disclose a delay circuit configured to receive a clock signal and to output a delayed clock signal.
Bindra et al. teach the deficiencies in e.g., FIG. 2A and accompanying disclosure, e.g., para. 0020, i.e., a delayed buffer may be used an electronic circuit such as logic circuit to assist (i.e., Kumar’s assist circuitry) a delayed path for a clock or data signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bindra et al. to the teaching of Kumar et al. such that a memory, as taught by Kumar et al., utilizes a delay circuit, as taught by Bindra et al., for the purpose of utilizing synchronous logic circuit in a memory device, thereby enhancing memory operations.
Kumar et al. and Bindra et al. do not explicitly disclose initiating a precharge operation on a bit line of the memory array; and activating the word line when the precharge operation is completed.
However, initialing a pre-charge operation on a bit line of the memory is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Frederick (US 2007/0159909), FIG. 3: precharge, and accompanying
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a pre-charge operation because these conventional technology are well established in the art of the memory devices.
Allowable Subject Matter
Claim 3 is rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 8 and 19, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights