Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 4, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed December 4, 2024 have been considered.
Claim Objections
Claims 9, 10, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, 10, 11 and 19 of U.S. Patent No. 12190938 [‘938]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘938
1. A driver, comprising: a driver circuit coupled to a word line; a reference circuit comprising a capacitor, the reference circuit being coupled to the driver circuit, the reference circuit being configured to lower a reference voltage from a first level to a second level; and a bias circuit coupled to the reference circuit, wherein the capacitor, the driver circuit, and the bias circuit are coupled to a reference node.
1. A memory driver, comprising: a word line driver circuit coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal; a reference circuit having a capacitor coupled to the reference node, the reference circuit being configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line; and a bias circuit coupled to the reference node and configured to regulate the lowered reference voltage at the reference node.
2. The driver of claim 1, wherein the reference circuit is coupled to an enable transistor, the enable transistor being coupled to the reference node and to an operating voltage node.
2. The memory driver of claim 1, wherein after the reference voltage is lowered to the second voltage level by the reference circuit, the bias circuit is enabled to regulate the reference voltage at the reference node.
3. The driver of claim 1, wherein the word line is coupled to the reference node via the driver circuit.
“…a word line driver circuit coupled to a word line and configured to selectively provide a reference voltage from a reference node…” - see claim 1.
4. The driver of claim 1, wherein the reference circuit further comprises a bias string coupled in parallel to the capacitor.
5. The memory driver of claim 1, wherein the reference circuit is configured to charge the capacitor at the reference node with an operating voltage, the reference circuit further comprises: a bias string coupled in parallel to the capacitor to limit a voltage across the capacitor at the first voltage level.
5. The driver of claim 4, wherein the reference circuit further comprises: a switch coupled in series with the capacitor, and a resistor coupled between the switch and the capacitor.
10. The memory driver of claim 9, wherein the capacitor trimming circuit comprises a switch coupled in series with a trimming capacitor, a series combination of the switch and the trimming capacitor is coupled in parallel with the capacitor, and the total capacitance coupled to the reference node is adjusted to a sum of the capacitance of the capacitor and a capacitance of the trimming capacitor when the switch is closed.
6. The driver of claim 1, wherein the driver circuit is configured to selectively provide the reference voltage from the reference node to the word line according to an input signal.
“…a word line driver circuit coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line…” – see claim 1.
7. The driver of claim 1, wherein: the reference circuit is configured to: store the reference voltage on the capacitor, and lower the reference voltage from the first level to the second level when the driver circuit provides the reference voltage.
11. A memory system, comprising: a memory array comprising a plurality of memory cells controlled by a plurality of word lines; and a memory driver, comprising: a word line driver circuit coupled to the plurality of word lines and configured to selectively provide a reference voltage from a reference node to a selected word line of the plurality of word lines according to an input signal; a reference circuit comprising a capacitor coupled to the reference node, the reference circuit being configured to store the reference voltage on the capacitor, to cause charge sharing according to a capacitance of the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line; and a bias circuit coupled to the reference node and configured to regulate the reference voltage after the reference voltage is provided from the reference node to the selected word line.
8. The driver of claim 7, wherein the reference circuit is configured to set the reference voltage between the first level and the second level by sharing the capacitor charge between the capacitor and an equivalent capacitance of the word line.
19. An operating method for operating a memory array, the memory array comprising a plurality of memory cells controlled by a plurality of word lines, the operating method comprising: storing a reference voltage on a capacitor and coupling the capacitor to a reference node to provide the reference voltage to the reference node; selectively providing the reference voltage to a selected word line of the plurality of word lines; lowering the reference voltage from a first voltage level to a second voltage level by voltage sharing between the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided from the reference node to the selected word line of the plurality of word lines; and regulating the lowered reference voltage at the reference node.
As can be seen from the above table, both, claim 1 of the application and claim 1 of the patent ‘938, have the following components in common:
Driver Circuit & Word Line: Both recitations include a driver circuit coupled to a word line (specified as a "word line driver circuit" in the ref phrase).
Reference Circuit & Capacitor: Both incorporate a reference circuit comprising a capacitor.
Voltage Lowering: Both define that the reference circuit is configured to lower a reference voltage from a first level to a second level.
Bias Circuit: Both include a bias circuit coupled to the reference circuit/node to regulate voltages.
Coupling: The ref phrase explicitly describes all three core components connecting to a reference node (which encompasses being coupled to each other), which anticipates the ap phrase's requirement that the capacitor, driver circuit, and bias circuit are coupled to a reference node.
The application claims fewer limitations (omitting the word line driver’s conditional
switching based on an input signal and the regulation of the lowered voltage), making it an obvious variation or broader recitation of the patent’s claim. Because the patent’s recitation describes the same structural architecture (and inherent functionality), granting a separate patent on the applied phrase would improperly extend the monopoly term for the same inventive concept.
With respect to claim 2, In memory and driver circuits, an “enable transistor” or “pass gate” is functionally required to selectively couple an operating voltage node (like (V_DD) or (V_CC}) to a reference node or capacitor to initiate voltage storage or lowering. The patent recitation states that its circuit is “configured to selectively provide a reference voltage from a reference node” and “store the reference voltage on the capacitor.” To selectively route this voltage and store charge onto the capacitive node, the hardware must employ a switching element, such as the claimed enable transistor, between the voltage supply node and the reference node.
For similar reasons, claims 3-8 are rejected over claims 1, 2, 5, 10, 11 and 19 of patent ‘938.
Claims 11-13 and 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-13 of U.S. Patent No. 12190938 [‘938]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘938
11. A system comprising: a memory array; and a driver, comprising: a word line driver circuit configured to selectively provide a reference voltage from a reference node to a selected word line of the memory array; a reference circuit comprising a capacitor coupled to the reference node, the reference circuit being configured to cause charge sharing according to a capacitance of the capacitor; and a bias circuit coupled to the reference node and configured to regulate the reference voltage.
11. A memory system, comprising: a memory array comprising a plurality of memory cells controlled by a plurality of word lines; and a memory driver, comprising: a word line driver circuit coupled to the plurality of word lines and configured to selectively provide a reference voltage from a reference node to a selected word line of the plurality of word lines according to an input signal; a reference circuit comprising a capacitor coupled to the reference node, the reference circuit being configured to store the reference voltage on the capacitor, to cause charge sharing according to a capacitance of the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line; and a bias circuit coupled to the reference node and configured to regulate the reference voltage after the reference voltage is provided from the reference node to the selected word line.
12. The system of claim 11, wherein the word line driver circuit is between the selected word line and the reference node and couples the word line with the reference node.
“…a memory driver, comprising:… and a bias circuit coupled to the reference node and configured to regulate the reference voltage…” – see claim 11…and, 13. The memory system of claim 12, wherein the bias circuit comprises a first switch and a second switch, the first switch is coupled between the reference node and an operating voltage terminal, and the second switch is coupled between the reference node and a ground voltage terminal, both the first switch and the second switch configured to close in response to an enable signal, and the bias circuit is configured to generate the reference voltage at the second voltage level through voltage division when the enable signal is enabled.
13. The system of claim 11, wherein the reference circuit is coupled to an enable transistor, the enable transistor being coupled to the reference node and to an operating voltage node.
See claim 11.
15. The system of claim 11, wherein the word line driver is configured to provide the reference voltage from the reference node to the word line in response to an input signal.
“…a word line driver circuit coupled to the plurality of word lines and configured to selectively provide a reference voltage from a reference node to a selected word line of the plurality of word lines according to an input signal…” – see claim 11.
16. The system of claim 15, wherein: the reference circuit is configured to: store the reference voltage on the capacitor, and lower the reference voltage from a first voltage level to a second voltage level when the driver circuit provides the reference voltage.
12. The memory system of claim 11, wherein the reference voltage is lowered from a first voltage level to a second voltage level through the charge sharing, a ratio of the second voltage level to the first voltage level is proportional to a ratio of a capacitance of the capacitor to a sum of the capacitance of the capacitor and the equivalent capacitance of the selected word line.
17. The system of claim 15, wherein: the memory array comprises a plurality of memory cells; the reference circuit is configured to cause the charge sharing according to the capacitance of the capacitor and an equivalent capacitance of the word line when the word line driver circuit provides the reference voltage from the reference node; the charge sharing lowers the reference voltage from a first voltage level to a second voltage level; and the bias circuit is configured to regulate the reference voltage after the reference voltage is provided from the reference node to the word line.
“…to cause charge sharing according to a capacitance of the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line; and a bias circuit coupled to the reference node and configured to regulate the reference voltage after the reference voltage is provided from the reference node to the selected word line.” – see claim 11.
As can be seen from the above table, both, claim 11 of the application and claim 11 of the patent ‘938, have the following components in common:
Driver Circuit & Word Line: Both recitations include a driver circuit coupled to a word line (specified as a "word line driver circuit" in the ref phrase).
Reference Circuit & Capacitor: Both incorporate a reference circuit comprising a capacitor.
Voltage Lowering: Both define that the reference circuit is configured to lower a reference voltage from a first level to a second level.
Bias Circuit: Both include a bias circuit coupled to the reference circuit/node to regulate voltages.
Coupling: The ref phrase explicitly describes all three core components connecting to a reference node (which encompasses being coupled to each other), which anticipates the ap phrase's requirement that the capacitor, driver circuit, and bias circuit are coupled to a reference node.
The application claims fewer limitations (omitting the word line driver’s conditional
switching based on an input signal and the regulation of the lowered voltage), making it an obvious variation or broader recitation of the patent’s claim. Because the patent’s recitation describes the same structural architecture (and inherent functionality), granting a separate patent on the applied phrase would improperly extend the monopoly term for the same inventive concept.
With respect to claim 13, In memory and driver circuits, an “enable transistor” or “pass gate” is functionally required to selectively couple an operating voltage node (like (V_DD) or (V_CC}) to a reference node or capacitor to initiate voltage storage or lowering. The patent recitation states that its circuit is “configured to selectively provide a reference voltage from a reference node” and “store the reference voltage on the capacitor.” To selectively route this voltage and store charge onto the capacitive node, the hardware must employ a switching element, such as the claimed enable transistor, between the voltage supply node and the reference node.
For similar reasons, claims 12 and 15-17 are rejected over claims 11-13 of patent ‘938.
Claims 18 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 12190938 [‘938]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘938
18. An apparatus comprising: a memory array comprising a plurality of word lines; and a memory driver, comprising: a driver circuit coupled to the plurality of word lines and configured to provide a reference voltage to at least one of the plurality of word lines according to an input signal; a reference circuit comprising a capacitor, the reference circuit being coupled to the driver circuit and configured to reduce the reference voltage from a high voltage level to an enabled voltage level, the enabled voltage level being determined by the capacitor, the high voltage level being determined based on an operating voltage; and a bias circuit coupled to the reference circuit, the bias circuit being configured to provide a second reference voltage at the enabled voltage level when the bias circuit is enabled.
18. The memory system of claim 11, wherein the capacitor is a first capacitor, the reference circuit comprises: a first reference circuit comprising the first capacitor, the first reference circuit being enabled by a first enable signal to provide a first reference voltage to the reference node, and lower the first reference voltage when the first reference voltage is provided by the word line driver circuit from the reference node to a first selected word line of the plurality of word lines; and a second reference circuit comprising a second capacitor, the second reference circuit being enabled by a second enable signal to provide a second reference voltage to the reference node, and lower the second reference voltage when the second reference voltage is provided by the word line driver circuit from the reference node to a second selected word line of the plurality of word lines.
19. The apparatus of claim 18, wherein: the driver circuit and the reference circuit are connected to a reference node set at the reference voltage; the driver circuit is between the plurality of word lines the reference node; the driver circuit couples the plurality of word lines with the reference node; and the reference circuit is coupled to an enable transistor, the enable transistor being coupled to the reference node and to an operating voltage node.
See claim 18.
As can be seen from the above table, both, claim 18 of the application and claim 18 of the patent ‘938, have the following components in common:
Driver Circuit & Word Line: Both recitations include a driver circuit coupled to a word line (specified as a "word line driver circuit" in the ref phrase).
Reference Circuit & Capacitor: Both incorporate a reference circuit comprising a capacitor.
Voltage Lowering: Both define that the reference circuit is configured to lower a reference voltage from a first level to a second level.
Bias Circuit: Both include a bias circuit coupled to the reference circuit/node to regulate voltages.
Coupling: The ref phrase explicitly describes all three core components connecting to a reference node (which encompasses being coupled to each other), which anticipates the ap phrase's requirement that the capacitor, driver circuit, and bias circuit are coupled to a reference node.
The application claims fewer limitations (omitting the word line driver’s conditional
switching based on an input signal and the regulation of the lowered voltage), making it an obvious variation or broader recitation of the patent’s claim. Because the patent’s recitation describes the same structural architecture (and inherent functionality), granting a separate patent on the applied phrase would improperly extend the monopoly term for the same inventive concept.
With respect to claim 19, The operational logic of connecting an enable/bias circuit to a reference node and an operating voltage node to regulate voltage is fully captured by the reference circuit's capacitor charge-sharing and bias-regulating architecture.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 9: The driver of claim 1, wherein the capacitor is a first capacitor; and the reference circuit comprises a trimming circuit coupled in parallel with the first capacitor, the trimming circuit comprising a switch and a second capacitor coupled in series.
-with respect to claim 10: The driver of claim 1, wherein: the word line driver is coupled to a plurality of word lines; the plurality of word lines are coupled to corresponding buffers within the driver circuit; each of the corresponding buffers comprise at least two inverters in series; a first of the at least two inverters is coupled to an operating voltage node, and a second of the at least two inverters is coupled to the reference node.
-with respect to claim 14: The system of claim 11, wherein the reference circuit further comprises: a bias string coupled in parallel to the capacitor; a switch coupled in series with the capacitor; and a resistor coupled between the switch and the capacitor.
-with respect to claim 20: The apparatus of claim 18, wherein: the plurality of word lines are coupled to a plurality of buffers; and each of the plurality of buffers comprises a first inverter coupled to an operating voltage and a second inverter coupled to the reference node.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 28, 2026
Prosecution Insights