Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed December 9, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 12
b. Pending: 1-20
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-7, 12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20260011383 A1) in view of Kanda et al. (US Pub. 20020196074 A1; “Kanda”) and Chung (US Pub. 20150310927 A1).
Regarding independent claim 1, Kim discloses a memory circuit (Fig. 1: electronic device 1; [0025]), comprising:
a non-volatile memory (nonvolatile memory 1120; [0027]);
a one-time-programmable memory (Fig. 3: OTP; [0068]: a plurality of OTP unit cells OTPC are arranged in the second area R2);
a sense amplifier (Fig. 2: sensing circuit 50; [0190]: The sensing circuit 50 may include the sense amplifier SA) coupled to the non-volatile memory and the one-time-programmable memory (per Fig. 2, sensing circuit 50 is coupled to memory cell array 10, which per Fig. 3 and [0068] includes the nonvolatile memory 1120 and the OTP);
a decoder (Fig. 2: row decoder 20 & column decoder 30; [0043]) coupled to an output of the control logic (per Fig. 2, decoders 20 and 30 are connected to outputs of control logic 80; [0043]); and
a controller for outputting a control signal to the control logic ([0052]: the control logic 80 may operate in response to a command CM D or control signals input from an external source. Examiner concludes that the external source is a controller) to select a first reference resistance for the sense amplifier from the decoder for a reading of bits from the one-time-programmable memory, and to select a second reference resistance for the sense amplifier from the decoder for a reading of bits from the non-volatile memory ([0008]: a first reference resistance for reading data for the memory cell or a second reference resistor having a second reference resistance for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance; claim 9: the first reference resistance or the second reference resistance is provided to the sense amplifier as a function of the word line selected to be connected to the memory cell and the word line selected to be connected to the OTP cell).
Kim does not disclose:
a digital register coupled to an output of the sense amplifier for storing reference resistance bits;
control logic coupled to an output of the digital register;
However, Kanda teaches:
a digital register (Fig. 24: register 50; [0136]) for storing reference resistance bits ([0136]: a register 50 serving as internal storing means for storing the resistance bit data determined by the determining part 49);
control logic (Fig. 22: control circuit 39) coupled to an output of the digital register ([0136]: In FIG. 24, the control circuit 39 of FIG. 22 comprises…a register 50. Examiner asserts that the control circuit 39 is coupled to the output of the register 50 due to the fact that the control circuit contains register 50 in its entirety);
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kanda to
Kim wherein the memory circuit comprises a digital register for storing reference resistance bits and control logic coupled to an output of the digital register in order to provide a circuit that adjusts a resistance in order to perform a voltage trimming function (Kanda, [0009]).
Also, Chung teaches:
a digital register (Fig. 9(b3): master latch 154; [0094]) coupled to an output of the sense amplifier (sense amplifier 153; [0094])
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Chung to
modified Kim wherein the memory circuit comprises a digital register coupled to an output of the sense amplifier in order to implement a low-pin-count non-volatile memory with a reduced footprint and which may include an OTP interface (Chung, [0014]).
Regarding claim 3, Kim, Kanda, and Chung together disclose all the limitations of claim 1, and further through Kim:
wherein a portion of the non-volatile memory (Fig. 1: nonvolatile memory 1120; [0027]) includes the one-time-programmable memory (per Fig. 2, nonvolatile memory 1120 contains memory cell array 10, and per Fig. 3, memory cell array 10 contains OTP in the second area R2; [0068]).
Regarding claim 4, Kim, Kanda, and Chung together disclose all the limitations of claim 1, and further through Kim:
wherein the controller outputs the control signal to the control logic ([0052])
Kim does not disclose:
controller outputs the control signal during a power-on-reset process
However, Chung teaches:
output the control signal during a power-on-reset process ([0076]: a Read Enable (RE) signal can be raised to sense and latch cells in a low-pin-count NVM to output Q in parallel or in serial. The RE can be triggered by a signal external to the low-pin-count NVM, or triggered by a Power-On Reset (POR) signal)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Chung to modified Kim wherein the control signal is output during a power-on-reset process in order to implement a low-pin-count non-volatile memory with a reduced footprint and which may include an OTP interface (Chung, [0014]).
Regarding claim 6, Kim, Kanda, and Chung together disclose all the limitations of claim 1, and further through Kim:
wherein the control logic (Fig. 2: 80) outputs an address to the decoder ([0046]: a row address R_ADDR and a row control signal R_CTRL supplied to the row decoder 20; [0047]: a column address C_ADDR and a column control signal C_CTRL supplied to the column decoder 30) for selecting a reference resistance from the decoder ([0008]).
Regarding claim 7, Kim, Kanda, and Chung together disclose all the limitations of claim 1. Claim 7 recites substantially the same subject matter as the last limitation of claim 1, and henceforth is rejected for the same reasons.
Independent claim 12 is substantially the same in claimed subject matter to
independent claim 1 and is rejected for the same reasons as independent claim 1.
Regarding claim 15, Kim, Kanda, and Chung together disclose all the limitations of claim 12. Claim 15 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 16, Kim, Kanda, and Chung together disclose all the limitations of claim 12. Claim 16 recites substantially the same limitations as claim 4, and henceforth is rejected for the same reasons.
Regarding claim 17, Kim, Kanda, and Chung together disclose all the limitations of claim 15. The second limitation of claim 17 is substantially the same as part of the last limitation of claim 1, and is thus rejected for the same reasons. Further, through Kanda:
receiving, by the controller, a reset signal ([0136]: In FIG. 24, the control circuit 39 of FIG. 22 comprises: a counter 48, controlled by a reset signal RST)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kanda to
modified Kim wherein the method comprises receiving, by the controller, a reset signal in order to provide a circuit that adjusts a resistance in order to perform a voltage trimming function (Kanda, [0009]).
Also, through Chung:
a reset signal indicating a start of the power-on-reset process (in reference to Fig. 13(c), per [0113]: generate a power-up reset (POR) signal in step 604. POR generates a first read pulse RE in step 606); and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Chung to modified Kim wherein the method comprises receiving a reset signal indicating a start of the power-on-reset process in order to implement a low-pin-count non-volatile memory with a reduced footprint and which may include an OTP interface (Chung, [0014]).
Regarding claim 18, Kim, Kanda, and Chung together disclose all the limitations of claim 16. Claim 18 recites exactly the same limitations as claim 7, and henceforth is rejected for the same reasons.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable
over Kim (US Pub. 20260011383 A1) in view of Kanda (US Pub. 20020196074 A1) and Chung (US Pub. 20150310927 A1) as applied to claims 1 and 12 above, respectively, and further in view of Choi et al. (US Pub. 20160093398 A1; “Choi”).
Regarding claim 2, Kim, Kanda, and Chung together disclose all the limitations of claim 1. Neither Kim, Kanda, nor Chung discloses:
wherein the first reference resistance is greater than the second reference resistance.
However, Choi teaches:
wherein the first reference resistance is greater than the second reference resistance ([0019]: in the case where the nonvolatile memory cell is an OTP (One-Time Programmable) cell…the second insulating layer has a first resistance value, in the case where the nonvolatile memory cell is used as the OTP cell, the second insulating layer has a second resistance value that is smaller than the first resistance value in the nonvolatile memory cell that is in a programmed state).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Choi to modified Kim wherein the first reference resistance is greater than the second reference resistance in order to provide a hybrid memory device that can be used as either an OTP memory or an MTP memory (Choi, [0006]).
Regarding claim 13, Kim, Kanda, and Chung together disclose all the limitations of claim 12. Claim 13 recites exactly the same limitations as claim 2, and henceforth is rejected for the same reasons.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable
over Kim (US Pub. 20260011383 A1) in view of Kanda (US Pub. 20020196074 A1) and Chung (US Pub. 20150310927 A1) as applied to claims 1 and 12 above, respectively, and further in view of Yoo et al. (US Pub. 20150279473 A1; “Yoo”).
Regarding claim 5, Kim, Kanda, and Chung together disclose all the limitations of claim 1. Neither Kim, Kanda, nor Chung discloses:
wherein the bits read from the one-time-programmable memory include trim fuse bits.
However, Yoo teaches:
wherein the bits read from the one-time-programmable memory include trim fuse bits ([0028]: FIG. 4 illustrates the conventional trim data read out method used to read out trim data stored in the OTP memory area of the memory array in the flash memory device of FIG. 1. Referring to FIG. 4, in the conventional trim data read out method, the trim data stored in the memory cells in the OTP memory area 45 are read out using the normal flash memory cell read out operation).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yoo to modified Kim wherein the bits read from the one-time-programmable memory include trim fuse bits in order to implement a trim data readout method that allows reading during power-up (Yoo, [0014]).
Regarding claim 14, Kim, Kanda, and Chung together disclose all the limitations of claim 12. Claim 14 recites exactly the same limitations as claim 5, and henceforth is rejected for the same reasons.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable
over Kim (US Pub. 20260011383 A1) in view of Kanda (US Pub. 20020196074 A1) and Chung (US Pub. 20150310927 A1) as applied to claims 1 and 12 above, respectively, and further in view of Tsai (US Pub. 20160104535 A1).
Regarding claim 8, Kim, Kanda, and Chung together disclose all the limitations of claim 1. Kim discloses:
the control signal output by the controller ([0052]).
Neither Kim, Kanda, nor Chung discloses:
wherein the control logic comprises a plurality of OR gates, wherein a first input of each OR gate of the plurality of OR gates receives the control signal
However, Tsai teaches:
wherein the control logic (Fig. 5A: controlling circuit 422; [0046]) comprises a plurality of OR gates ([0046]: The controlling circuit 422 comprises a first sense amplifier SAe, a second sense amplifier SAp and plural OR gates), wherein a first input of each OR gate of the plurality of OR gates receives the control signal (control signal C; [0047])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tsai to modified Kim wherein the control logic comprises a plurality of OR gates, wherein a first input of each OR gate of the plurality of OR gates receives the control signal in order to implement a nonvolatile memory array with differential cells for which the storing state of erased differential cells can be successfully determined via a read operation (Tsai, [0024]).
Regarding claim 19, Kim, Kanda, and Chung together disclose all the limitations of claim 12. Claim 19 recites substantially the same limitations as claim 8, and henceforth is rejected for the same reasons.
Allowable Subject Matter
Claims 9-11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Park et al. (US Pub. 20230238069 A1): paras. [0047], [0058], [0090], [0094], [0137], Fig. 1A, and Fig. 2 are relevant to claims 1 and 12.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.R.A./Examiner, Art Unit 2824
6/27/2026
/PHO M LUU/Primary Examiner, Art Unit 2824
Prosecution Insights