DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 9, 12-15 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-11, 13, and 14 of U.S. Patent No. 12,165,722. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 2, 9, 12-15 and 17-20 would have been obvious over claims 9-11, 13 and 14 of the patent.
Regarding claim 1, claims 9 and 10 of the patent recite a memory circuit comprising:
a first non-volatile memory (NVM) device (claim 9, line 2);
a second NVM device (claim 10, line 2); and
a driver circuit comprising a first power switch (claim 9, line 6, a first HV power switch), a second power switch (claim 10, line 4, a second HV power switch), a first driver, and a second driver, wherein
the first power switch is configured to generate a first power signal (a first power HV power signal),
the second power switch is configured to generate a second power signal (a second HV power signal),
the first driver is configured to output a first activation signal to the first NVM device responsive to the first power signal (claim 9, lines 14-17),
the second driver is configured to output a second activation signal to the second NVM device responsive to the second power signal (claim 10, lines 14-17),
the driver circuit is configured to output a third activation signal having a voltage less than that of the first activation signal to the first NVM device,
the driver circuit is configured to output a fourth activation signal having a voltage less than that of the second activation signal to the second NVM device,
the first activation signal and the third activation signal are based on a first enable signal, and
the second activation signal and the fourth activation signal are based on a second enable signal.
It would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claim 1 of the application and the memory circuit of claim 9 of the patent are identical in structure; therefore, the differences between claim 1 of the application and claim 9 of the patent are only functional limitations.
Regarding claim 2, claims 13 and 14 of the patent recite the memory circuit of claim 1, wherein each of the first driver and the second driver comprises:
a power signal node coupled to the corresponding first or second power switch;
an analog ground node coupled to the corresponding first or second power switch;
an output node coupled to the corresponding first or second NVM device;
a ground reference node configured to have a ground voltage level;
a latch circuit (cross-coupled inverters) coupled between the power signal node and the analog ground node;
first and second PMOS transistors coupled in series between the power signal node and the output node; and
first and second NMOS transistors coupled in series between the output node and the ground reference node (claim 14).
Regarding claim 9, claims 9 and 10 of the patent recite the memory circuit of claim 1, wherein the driver circuit further comprises:
a third driver (claim 9, line 3, one of the plurality of first HV drivers) configured to output the third activation signal; and
a fourth driver (claim 10, line 3, one of the plurality of second HV drivers) configured to output the fourth activation signal.
Regarding claim 12, claims 9 and 10 of the patent recites a memory circuit comprising:
a first bank of non-volatile memory (NVM) devices (claim 9, line 2);
a second bank of NVM devices (claim 10, line 2);
a first HV power switch configured to provide a first high-voltage (HV) power signal having a first voltage magnitude (claim 9, lines 9-10);
a second HV power switch configured to provide a second HV power signal having a second voltage magnitude less than the first voltage magnitude (claim 10, lines 9-10); and
a driver circuit adjacent to the first and second banks of NVM devices, wherein the driver circuit is configured to:
receive the first and second HV power signals (claim 9, lines 14-18 and claim 10, lines 14-18), and
in response to an address signal having a configuration corresponding to a first NVM device in the first bank of NVM devices,
output a first HV activation signal to the first NVM device, the first HV activation signal having the first voltage magnitude (claim 9, lines 14-16), and output a second HV activation signal to the second bank of NVM devices, the second HV activation signal having a third voltage magnitude equal to or less than the second voltage magnitude (claim 10, lines 14-17).
Regarding claim 13, claim 11 of the patent recites the memory circuit of claim 12, wherein the driver circuit comprises:
a decoder configured to generate an enable signal responsive to the address signal;
a first driver configured to output the first HV activation signal to the first NVM device responsive to the first HV power signal and the enable signal; and
a second driver configured to output the second HV activation signal to the second bank of NVM devices responsive to the second HV power signal and the enable signal,
wherein the second HV activation signal has the third voltage magnitude equal to the second voltage magnitude.
Regarding claim 14, claim 11 of the patent recites the memory circuit of claim 12, wherein the driver circuit comprises:
first and second decoders configured to generate respective first and second enable signals responsive to the address signal;
a first driver configured to output the first HV activation signal to the first NVM device responsive to the first HV power signal and the first enable signal; and
a second driver configured to output the second HV activation signal to the second bank of NVM devices responsive to the second HV power signal and the second enable signal,
wherein the second HV activation signal has the third voltage magnitude equal to a ground voltage level.
Regarding claim 15, claims 9, 10 and 13 of the patent recite the memory circuit of claim 12, wherein
the first HV power switch is further configured to, when the first HV power signal has the first voltage magnitude, provide an analog ground signal having a fourth voltage magnitude between the first voltage magnitude and a ground voltage level.
Regarding claims 17-20, it would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claims 9-11, 13, and 14 of the patent is used to perform the method of claims 17-20 of the instant application.
Claims 1, 9, 12 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 11,791,006 Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 9, 12 and 17-20 would have been obvious over claim 10 of the patent.
Regarding claim 1, claim 10 of the patent recite a memory circuit comprising:
a first non-volatile memory (NVM) device (claim 10, lines 2-3);
a second NVM device (claim 10, lines 2-3); and
a driver circuit (claim 10, line 4) comprising a first power switch, a second power switch, a first driver, and a second driver, wherein
the first power switch is configured to generate a first power signal (claim 10, lines 16-18),
the second power switch is configured to generate a second power signal (clam 10, lines 19-21),
the first driver is configured to output a first activation signal to the first NVM device responsive to the first power signal (claim 10, lines 22-25),
the second driver is configured to output a second activation signal to the second NVM device responsive to the second power signal (claim 10, lines 26-29),
the driver circuit is configured to output a third activation signal having a voltage less than that of the first activation signal to the first NVM device,
the driver circuit is configured to output a fourth activation signal having a voltage less than that of the second activation signal to the second NVM device,
the first activation signal and the third activation signal are based on a first enable signal, and
the second activation signal and the fourth activation signal are based on a second enable signal.
It would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claim 1 of the application and the memory circuit of claim 10 of the patent are identical in structure; therefore, the differences between claim 1 of the application and claim 10 of the patent are only functional limitations.
Regarding claim 9, claim 10 of the patent recites the memory circuit of claim 1, wherein the driver circuit further comprises:
a third driver (claim 10, line 4, one driver in the first plurality of drivers) configured to output the third activation signal; and
a fourth driver (claim 10, line 4, one driver in the second plurality of drivers) configured to output the fourth activation signal.
Regarding claim 12, claim 10 of the patent recites a memory circuit comprising:
a first bank of non-volatile memory (NVM) devices (claim 10, lines 2-3);
a second bank of NVM devices (claim 10, lines 2-3);
a first HV power switch configured to provide a first high-voltage (HV) power signal having a first voltage magnitude (claim 10, lines 5-6);
a second HV power switch configured to provide a second HV power signal having a second voltage magnitude less than the first voltage magnitude (claim 10, lines 5-6); and
a driver circuit adjacent to the first and second banks of NVM devices, wherein the driver circuit is configured to:
receive the first and second HV power signals, and
in response to an address signal having a configuration corresponding to a first NVM device in the first bank of NVM devices,
output a first HV activation signal to the first NVM device, the first HV activation signal having the first voltage magnitude (claim 10, lines 22-23), and output a second HV activation signal to the second bank of NVM devices (claim 10, lines 26-27), the second HV activation signal having a third voltage magnitude equal to or less than the second voltage magnitude.
It would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claim 12 of the application and the memory circuit of claim 10 of the patent are identical in structure; therefore, the differences between claim 12 of the application and claim 10 of the patent are only functional limitations.
Regarding claims 17-20, it would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claim 10 of the patent is used to perform the method of claims 17-20 of the instant application.
Claims 1, 9-14 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 8-10 of U.S. Patent No. 11,450,395 Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 9-14 and 16-20 would have been obvious over claims 1, 2 and 8-10 of the patent.
Regarding claims 1 and 12, claims 1 and 2 of the patent recite a memory circuit comprising:
a first non-volatile memory (NVM) device (claim 1, line 2);
a second NVM device (claim 2, line 2); and
a driver circuit comprising a first power switch (claim 1, lines 9-10), a second power switch (claim 2, lines 5-6), a first driver (claim 1, line 13), and a second driver (claim 2, line 14), wherein
the first power switch is configured to generate a first power signal (claim 1, lines 16-17),
the second power switch is configured to generate a second power signal (claim 2, lines 17-18),
the first driver is configured to output a first activation signal to the first NVM device responsive to the first power signal (claim 1, lines 14-16),
the second driver is configured to output a second activation signal to the second NVM device responsive to the second power signal (claim 10, lines 15-17),
the driver circuit is configured to output a third activation signal having a voltage less than that of the first activation signal to the first NVM device,
the driver circuit is configured to output a fourth activation signal having a voltage less than that of the second activation signal to the second NVM device,
the first activation signal and the third activation signal are based on a first enable signal, and
the second activation signal and the fourth activation signal are based on a second enable signal.
It would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claims 1 and 12 of the application and the memory circuit of claims 1 and 2 of the patent are identical in structure; therefore, the differences between claims 1 and 12 of the application and claims 1 and 2 of the patent are only functional limitations.
Regarding claim 9, claims 1 and 2 of the patent recite the memory circuit of claim 1, wherein the driver circuit further comprises:
a third driver configured to output the third activation signal (claim 1, line 13-14); and
a fourth driver configured to output the fourth activation signal (claim 2, lines 14-15).
Regarding claim 10, claim 8 of the patent recites the memory circuit of claim 9, wherein
the first NVM device comprises a first program transistor comprising a gate coupled to the first driver and a first read transistor comprising a gate coupled to the third driver, and
the second NVM device comprises a second program transistor comprising a gate coupled to the second driver and a second read transistor comprising a gate coupled to the fourth driver.
Regarding claim 11, claims 1 and 2 of the patent recite the memory circuit of claim 9, wherein the driver circuit further comprises one of:
a decoder coupled to each of the first through fourth drivers and configured to generate the first and second enable signals as a same enable signal based on one or more address signals; or
a first decoder coupled to each of the first and third drivers and configured to generate the first enable signal based on the one or more address signals; and
a second decoder coupled to each of the second and fourth drivers and configured to generate the second enable signal based on the one or more address signals.
Regarding claim 12, claims 9 and 10 of the patent recites a memory circuit comprising:
a first bank of non-volatile memory (NVM) devices (claim 9, line 2);
a second bank of NVM devices (claim 10, line 2);
a first HV power switch configured to provide a first high-voltage (HV) power signal having a first voltage magnitude (claim 9, lines 9-10);
a second HV power switch configured to provide a second HV power signal having a second voltage magnitude less than the first voltage magnitude (claim 10, lines 9-10); and
a driver circuit adjacent to the first and second banks of NVM devices, wherein the driver circuit is configured to:
receive the first and second HV power signals (claim 9, lines 14-18 and claim 10, lines 14-18), and
in response to an address signal having a configuration corresponding to a first NVM device in the first bank of NVM devices,
output a first HV activation signal to the first NVM device, the first HV activation signal having the first voltage magnitude (claim 9, lines 14-16), and output a second HV activation signal to the second bank of NVM devices, the second HV activation signal having a third voltage magnitude equal to or less than the second voltage magnitude (claim 10, lines 14-17).
Regarding claim 13, claims 1 and 2 of the patent recite the memory circuit of claim 12, wherein the driver circuit comprises:
a decoder configured to generate an enable signal responsive to the address signal;
a first driver configured to output the first HV activation signal to the first NVM device responsive to the first HV power signal and the enable signal; and
a second driver configured to output the second HV activation signal to the second bank of NVM devices responsive to the second HV power signal and the enable signal,
wherein the second HV activation signal has the third voltage magnitude equal to the second voltage magnitude.
Regarding claim 14, claims 1 and 2 of the paten recite the memory circuit of claim 12, wherein the driver circuit comprises:
first and second decoders configured to generate respective first and second enable signals responsive to the address signal;
a first driver configured to output the first HV activation signal to the first NVM device responsive to the first HV power signal and the first enable signal; and
a second driver configured to output the second HV activation signal to the second bank of NVM devices responsive to the second HV power signal and the second enable signal,
wherein the second HV activation signal has the third voltage magnitude equal to a ground voltage level.
Regarding 16, claim 8 of the patent recites the memory circuit of claim 12, wherein each NVM device of the first and second banks of NVM devices comprises:
a program transistor comprising a gate configured to receive the corresponding first or second activation signal; and
a read transistor comprising a gate configured to receive a corresponding third or fourth activation signal from the driver circuit.
Regarding claims 17-20, it would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claims 1, 2 and 8-10 of the patent is used to perform the method of claims 17-20 of the instant application.
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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