DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicant’s amendment submitted on July 07, 2026. In virtue of this amendment, claims 1-20 are now pending in the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/08/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Terminal Disclaimer
The terminal disclaimer filed on 07/07/2026 disclaiming the terminal portion of any patent granted on this application has been disapproved since the title of the invention is missing on the top of the TD form.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 8-12 and 15-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5, 7 and 10 of U.S. Patent No. 12,193,138.
Although the claims at issue are not identical, they are not patentably distinct from each other because the above indicated claims of the instant application are either anticipated by, or would have been obvious over, the above identified claims of the above patent, including:
As claim 1: A matchless plasma source comprising: a signal generator configured to generate a square wave signal; a gate driver circuit coupled to the signal generator to output a plurality of reversely synchronized signals based on the square wave signal; and a tree circuit coupled to the gate driver circuit, wherein the tree circuit includes a plurality of half-bridge circuits to receive the plurality of reversely synchronized signals, wherein the plurality of reversely synchronized signals are received to output an amplified square waveform (see claim 1 of the above patent such that a tree circuit and a H-bridge circuit are both having a plurality of half-bridge circuits thereof).
As claim 2: The matchless plasma source of claim 1, wherein the square wave signal is a digital waveform that pulses between a first logic level and a second logic level (see claim 7 of the above patent).
As claim 3: The matchless plasma source of claim 1, wherein the plurality of reversely synchronized signals include a first synchronized signal and a second synchronized signal, wherein the first synchronized signal has a high power level during a time period in which the second synchronized signal has a low power level and the first synchronized signal has a low power level during a time period in which the second synchronized signal has a high power level (see claim 7 of the above patent).
As claim 4: The matchless plasma source of claim 1, wherein the plurality of half-bridge circuits include a first half-bridge circuit and a second half-bridge circuit, wherein the gate driver circuit includes a first gate driver and a second gate driver, wherein the first gate driver is coupled to the first and second half-bridge circuits and the second gate driver is coupled to the first and second half-bridge circuits (see claim 5 of the above patent).
As claim 5: The matchless plasma source of claim 4, wherein the first half-bridge circuit includes a first transistor and a second transistor, and the second half-bridge circuit includes a third transistor and a fourth transistor, wherein the first gate driver is coupled to the first transistor and the third transistor, and the second gate driver is coupled to the second transistor and the fourth transistor (see claim 2 of the above patent).
As claim 8: A plasma system comprising: a matchless plasma source including: a signal generator configured to generate a square wave signal; a gate driver circuit coupled to the signal generator to output a plurality of reversely synchronized signals based on the square wave signal; and a tree circuit coupled to the gate driver circuit, wherein the tree circuit includes a plurality of half-bridge circuits to receive the plurality of reversely synchronized signals, wherein the plurality of reversely synchronized signals are received to output an amplified square waveform; a reactive circuit coupled to the tree circuit for receiving the amplified square waveform to output a sinusoidal radio frequency (RF) waveform; and a plasma chamber coupled to the matchless plasma source to receive the sinusoidal RF waveform (see claim 1 of the above patent).
As claim 9: The matchless plasma source of claim 1, wherein the square wave signal is a digital waveform that pulses between a first logic level and a second logic level (see claim 7 of the above patent).
As claim 10: The matchless plasma source of claim 1, wherein the plurality of reversely synchronized signals include a first synchronized signal and a second synchronized signal, wherein the first synchronized signal has a high power level during a time period in which the second synchronized signal has a low power level and the first synchronized signal has a low power level during a time period in which the second synchronized signal has a high power level (see claim 7 of the above patent).
As claim 11: The matchless plasma source of claim 1, wherein the plurality of half-bridge circuits include a first half-bridge circuit and a second half-bridge circuit, wherein the gate driver circuit includes a first gate driver and a second gate driver, wherein the first gate driver is coupled to the first and second half-bridge circuits and the second gate driver is coupled to the first and second half-bridge circuits (see claim 5 of the above patent).
As claim 12: The matchless plasma source of claim 4, wherein the first half-bridge circuit includes a first transistor and a second transistor, and the second half-bridge circuit includes a third transistor and a fourth transistor, wherein the first gate driver is coupled to the first transistor and the third transistor, and the second gate driver is coupled to the second transistor and the fourth transistor (see claim 2 of the above patent).
As claim 15: A method comprising: generating, by a signal generator of a matchless plasma source, a square wave signal; outputting, from a gate driver circuit of the matchless plasma source, a plurality of reversely synchronized signals based on the square wave signal; and receiving, by a plurality of half-bridge circuits of a tree structure, the plurality of reversely synchronized signals, wherein the plurality of reversely synchronized signals are received to output an amplified square waveform, wherein the tree structure is of the matchless plasma source (see claims 1 and 10 of the above patent).
As claim 16: The method of claim 15, wherein the square wave signal is a digital waveform that pulses between a first logic level and a second logic level (see claim 7 of the above patent).
As claim 17: The method of claim 15, wherein the plurality of reversely synchronized signals include a first synchronized signal and a second synchronized signal, wherein the first synchronized signal has a high power level during a time period in which the second synchronized signal has a low power level and the first synchronized signal has a low power level during a time period in which the second synchronized signal has a high power level (see claim 7 of the above patent).
As claim 18: The method of claim 15, wherein the plurality of half-bridge circuits include a first half-bridge circuit and a second half-bridge circuit, wherein the gate driver circuit includes a first gate driver and a second gate driver, wherein the first gate driver is coupled to the first and second half-bridge circuits and the second gate driver is coupled to the first and second half-bridge circuits (see claim 5 of the above patent).
As claim 19: The method of claim 18, wherein the first half-bridge circuit includes a first transistor and a second transistor, and the second half-bridge circuit includes a third transistor and a fourth transistor, wherein the first gate driver is coupled to the first transistor and the third transistor, and the second gate driver is coupled to the second transistor and the fourth transistor (see claim 2 of the above patent).
Allowable Subject Matter
Claims 6-7, 13-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 07/07/2026 have been fully considered but they are not persuasive.
The terminal disclaimer filed on 07/07/2026 has been disapproved since the title of the invention is missing on the top of the TD form; and thus, claims 1-20 would be allowable if overcome the double patenting rejection set forth above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art Kim et al. – US 9,704,690
Prior art Umehara et al. – US 9,640,368
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUNG X LE whose telephone number is (571)272-6010. The examiner can normally be reached Monday to Friday from 10am to 6pm.
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/TUNG X LE/Primary Examiner, Art Unit 2845 August 23, 2026
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