DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species E, claims 1-20 in the reply filed on 05/28/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/19/2025, 06/10/2025, 04/28/2026, and 07/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “a vertical level same as a vertical level” in claim 1 is a relative term which renders the claim indefinite. The term “a vertical level same as a vertical level” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between the top surface of the bit line contact and the top surface of the substrate is not clearly defined.
The term “substantially coplanar” in claim 5 is a relative term which renders the claim indefinite. The term “substantially coplanar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between the bottom surface of the bit line bottom electrode and the top surface of the bit line contact, the bottom surface of the bit line top electrode with a top surface of the bit line bottom electrode, and the bottom surface of the bit line mask pattern and the top surface of the bit line top electrode is not clearly defined.
The term “substantially coplanar” in claim 6 is a relative term which renders the claim indefinite. The term “substantially coplanar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between the bottom surface of the is not clearly defined.
The term “substantially coplanar” in claim 7 is a relative term which renders the claim indefinite. The term “substantially coplanar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between the line top electrode, the bit line mask pattern, and the bit line spacer is not clearly defined.
The term “substantially coplanar” in claim 15 is a relative term which renders the claim indefinite. The term “substantially coplanar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between the bottom surface of the bit line bottom electrode and the top surface of a bit line contact, a bottom surface of the bit line top electrode and a top surface of the bit line bottom electrode, and a bottom surface of the bit line mask pattern and a top surface of the bit line top electrode is not clearly defined.
The term “substantially coplanar” in claim 16 is a relative term which renders the claim indefinite. The term “substantially coplanar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between a top surface of the bit line spacer and a top surface of the bit line mask pattern, and a bottom surface of the bit line spacer and a bottom surface of the bit line contact is not clearly defined.
The term “substantially coplanar” in claim 17 is a relative term which renders the claim indefinite. The term “substantially coplanar” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relationship between the sidewalls of the bit line contact, the bit line bottom electrode, the bit line top electrode, the bit line mask pattern, and the bit line spacer are not clearly defined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102 as being anticipated by Kim et al. ( US 12,191,364 B2; hereinafter Kim )
Regarding claim 11, Kim teaches a semiconductor device, comprising: a substrate ( Figs. 1 to 2D substrate 101 ); a gate dielectric ( Fig. 2B gate dielectric 110 ) embedded within the substrate ( as shown in Fig. 2B ); a gate electrode ( Fig. 2B gate electrode 120 ) spaced apart from the substrate by the gate dielectric ( as shown in Fig. 2B); a dielectric structure ( Col. 7 lines 3-10 the gate dielectric layer 110 may include a fluorine-containing gate dielectric layer 110F and a fluorine-free gate dielectric layer 110U. The fluorine-containing gate dielectric layer 110F may be a layer including the first and second interfaces F1 and F2, and the fluorine-free gate dielectric layer 110U may be a layer not including the first and second interfaces F1 and F2 ) disposed over the gate electrode ( Fig. 2B #120 ), wherein the dielectric structure includes a step profile ( Fig. 2B areas 110U and 110F ); a bit line ( Fig. 2A #140 ) positioned in a top surface of the substrate ( Fig. 2A #101 ) and between two of the gate electrodes ( Fig. 2A #120 ); a conductive plug ( Fig. 2A #150 ) positioned on the substrate ( Fig. 2A #101 ) and electrically connected to a doped region ( Fig. 2A #108 ) of the substrate ( Fig. 2A #101 ), wherein the conductive plug ( Fig. 2A #150 ) includes a first part disposed on the substrate ( Fig. 2A #101 ) and a second part disposed on the first part ( as shown in Fig. 2A #150 is continuous and connected to the substrate and the dielectric structure ) and in the dielectric structure ( as shown in Fig. 2A 110 overlaps 150 ); and a capacitor ( Fig. 2A #160 ) disposed over and electrically connected to the conductive plug ( Fig. 2A #150 ).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Yu et al.; US 11,881,507 B2; 07/2022
Claim 1: Kim discloses a semiconductor device, comprising: a substrate ( Fig. 2C substrate 101 ) with a top surface ( Fig. 2C top of 101 ), wherein the substrate includes an active area ( Fig. 2C active region 104 ) comprising an upper region ( Fig. 2C first and second doped regions 107 and 108 ) and a lower region ( Fig. 2C #104; Col. 3 lines 58 – 61 The bottom surfaces of the first and second doped regions 107 and 108 may be located at a predetermined depth from the top surface of the active region 104 ), wherein the upper region contains a plurality of doped regions ( Col. 3 lines 51-53 The first and second doped regions 107 and 108 are regions doped with conductive dopants ); and a bit line ( Fig. 2C bit line structure 140 ) positioned in and protruding from the active area ( Fig. 2C #107 ), wherein the bit line comprises a bit line contact located in the upper region of the active area ( Fig. 2C #142 ), and wherein a top surface of the bit line contact is at a vertical level same as a vertical level of the top surface of the substrate ( as shown in Fig. 2C the top surface of the bit line is parallel to the top surface of the substrate ).
Kim does not appear to disclose a dielectric layer at least partially embedded within the substrate, wherein the dielectric layer includes a first portion with a first thickness and a second portion with a second thickness less than the first thickness; a gate electrode spaced apart from the substrate by the first portion of the dielectric layer.
However, Yu teaches a dielectric layer ( Fig. 26A dielectric layer 284A ) at least partially embedded ( as shown in Fig. 26A ) within the substrate ( Fig. 26A substrate 202 ), wherein the dielectric layer ( Fig. 26A #284A ) includes a first portion with a first thickness ( Col. 14 lines 9 – 14 a top portion of the dielectric layer 284A that seals the air gap 282 has a thickness less than that of the bottom portion of the dielectric layer 284A; first portion is the top portion ) and a second portion with a second thickness less than the first thickness ( as discussed above; second portion is the bottom portion ); a gate electrode ( Fig. 21A gate electrode 264 ) spaced apart from the substrate ( Fig. 21A #202 ) by the first portion of the dielectric layer ( Fig. 21A #269 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yu with Kim to implement a dielectric layer at least partially embedded within the substrate, wherein the dielectric layer includes a first portion with a first thickness and a second portion with a second thickness less than the first thickness; a gate electrode spaced apart from the substrate by the first portion of the dielectric layer because this approach simultaneously improves electrical isolation, gate modulation, mechanical robustness, and thermal performance.
Claim 2: Kim and Yu disclose the semiconductor device of claim 1 ( as discussed above).
Kim teaches the bit line ( Fig. 2A #140 ) is positioned between two of the gate electrodes ( Fig. 2A gate electrodes 120 ).
Claim 3: Kim and Yu disclose the semiconductor device of claim 2 ( as discussed above),
Kim teaches the bit line ( Fig. 2C #140 ) is configured to electrically connect one of the doped regions ( Fig. 2C #170 ) to a bit line structure ( Col. 5 lines 43-45 The bit line structure 140 may be connected to the first doped region 107 by passing through the hard mask layer 109 ).
Claim 4 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Yu et al.; US 11,881,507 B2; 07/2022 as it relates to claim 3 above and further in view of Choi et al.; US 2022/0028860 A1; 03/2021
Claim 4: Kim and Yu disclose the semiconductor device of claim 3 ( as discussed above).
Neither Kim nor Yu appear to disclose the bit line comprises a bit line bottom electrode, a bit line top electrode, a bit line mask pattern, and a bit line spacer.
However, Choi teaches the bit line ( Fig. 3: line structures LST ) comprises a bit line bottom electrode ( Fig. 3 conductive pattern CP ), a bit line top electrode ( Fig. 3 bit line BL ), a bit line mask pattern ( [0038] Each of the line structures LST may include a conductive pattern CP, a barrier pattern BP, a bit line BL, and a mask pattern 1VIP, which are sequentially stacked ), and a bit line spacer ( Fig. 3 spacers SP ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Choi with Kim and Yu to implement the bit line comprises a bit line bottom electrode, a bit line top electrode, a bit line mask pattern, and a bit line spacer because this approach minimizes contact resistance and enhances electrical conductivity while facilitating barrier protection and alignment in 3D architectures.
Claims 5-7 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Yu et al.; US 11,881,507 B2; 07/2022 and Choi et al.; US 2022/0028860 A1; 03/2021 as it relates to claim 4 above and further in view of Huang; US 2021/0074639 A1; 09/2019
Claim 5: Kim, Yu, and Choi disclose the semiconductor device of claim 4 ( as discussed above).
Neither Kim nor Yu nor Choi appear to disclose a bottom surface of the bit line bottom electrode is substantially coplanar with the top surface of the bit line contact; a bottom surface of the bit line top electrode is substantially coplanar with a top surface of the bit line bottom electrode; and a bottom surface of the bit line mask pattern is substantially coplanar with a top surface of the bit line top electrode.
However, Huang teaches a bottom surface of the bit line bottom electrode ( Fig. 1: bit line bottom electrode 507 ) is substantially coplanar with the top surface of the bit line contact ( Fig. 1: bit line contact 505 ); a bottom surface of the bit line top electrode ( Fig. 1: bit line top electrode 509 ) is substantially coplanar with a top surface of the bit line bottom electrode ( Fig. 1 #507 ); and a bottom surface of the bit line mask pattern ( Fig. 1: bit line mask 511 ) is substantially coplanar with a top surface of the bit line top electrode ( Fig. 1 #509 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Kim, Yu, and Choi to implement a bottom surface of the bit line bottom electrode is substantially coplanar with the top surface of the bit line contact; a bottom surface of the bit line top electrode is substantially coplanar with a top surface of the bit line bottom electrode; and a bottom surface of the bit line mask pattern is substantially coplanar with a top surface of the bit line top electrode because this approach influences electrical performance, reliability, and mechanical stability.
Claim 6: Kim, Yu, Choi, and Huang disclose the semiconductor device of claim 5 ( as discussed above).
Neither Kim nor Yu nor Choi appear to disclose a top surface of the bit line spacer is substantially coplanar with a top surface of the bit line mask pattern, and a bottom surface of the bit line spacer is substantially coplanar with a bottom surface of the bit line contact.
However, Huang teaches a top surface of the bit line spacer ( Fig. 1 bit line spacers 513 ) is substantially coplanar with a top surface of the bit line mask pattern ( Fig. 1 bit line mask 511 ), and a bottom surface of the bit line spacer ( Fig. 1 #513 ) is substantially coplanar with a bottom surface of the bit line contact ( Fig. 1 #505 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Kim, Yu, and Choi to implement a top surface of the bit line spacer is substantially coplanar with a top surface of the bit line mask pattern, and a bottom surface of the bit line spacer is substantially coplanar with a bottom surface of the bit line contact because this approach integrates process simplicity, alignment fidelity, electrical uniformity, and device reliability.
Claim 7: Kim, Yu, Choi, and Huang disclose the semiconductor device of claim 6 ( as discussed above).
Neither Kim nor Yu nor Choi appear to disclose sidewalls of the bit line contact, the bit line bottom electrode, the bit line top electrode, the bit line mask pattern, and the bit line spacer are substantially coplanar.
However, Huang teaches sidewalls of the bit line contact ( Fig. 1 #505 ), the bit line bottom electrode ( Fig. 1 #507 ), the bit line top electrode ( Fig. 1 #509 ), the bit line mask pattern ( Fig. 1 #511 ), and the bit line spacer ( Fig. 1 #513 ) are substantially coplanar ( as shown in Fig. 1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Kim, Yu, and Choi to implement sidewalls of the bit line contact, the bit line bottom electrode, the bit line top electrode, the bit line mask pattern, and the bit line spacer are substantially coplanar because this approach ensures electrical robustness, reduces parasitic effects, and compensates for fabrication variability.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Yu et al.; US 11,881,507 B2; 07/2022 as it relates to claim 1 above and further in view of Lee et al.; US 12,696,437 B2; 11/2023
Claim 8: Kim and Yu disclose the semiconductor device of claim 1 ( as discussed above ).
Kim discloses further comprising: a conductive plug ( Fig. 2A storage node contact plugs 150 ) positioned on the substrate ( Fig. 2A #101 ) and configured to electrically connect to one of the doped regions of the active area ( Fig. 2A #108 ); a capacitor electrode landing pad ( Fig. 2A capacitor 160 ) disposed over and covering the conductive plug ( as shown in Fig. 2A ).
Neither Kim nor Yu appear to disclose a capacitor structure disposed over the capacitor electrode landing pad and electrically connected to the conductive plug.
However, Lee teaches a capacitor structure (Fig. 2A capacitor structure 80 ) disposed over the capacitor electrode landing pad ( Fig. 2A landing pad 69 ) and electrically connected ( Col. 8 lines 61-65 The capacitor structure 80 may be electrically connected to the landing pad 69 and the contact plug 60 ) to the conductive plug ( Fig. 2A contact plug 60 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Kim and Yu to implement a capacitor structure disposed over the capacitor electrode landing pad and electrically connected to the conductive plug because this approach ensures self-aligned, high-precision fabrication.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Yu et al.; US 11,881,507 B2; 07/2022 and Lee et al.; US 12,696,437 B2; 11/2023 as it relates to claim 8 above and further in view of Chiu et al.; US 2025/0098187 A1; 09/2023
Claim 9: Kim, Yu, and Lee disclose the semiconductor device of claim 8 ( as discussed above).
Neither Kim nor Yu appear to disclose the capacitor structure comprises: a capacitor bottom electrode disposed over the capacitor electrode landing pad; a capacitor top electrode disposed over the capacitor bottom electrode; and a capacitor dielectric disposed between the capacitor bottom electrode and the capacitor top electrode, wherein the capacitor bottom electrode includes a lower portion disposed over the capacitor electrode landing pad and an upper portion disposed over the lower portion.
Lee discloses the capacitor structure comprises: a capacitor bottom electrode ( Fig. 2A: lower electrode 82 ) disposed over the capacitor electrode landing pad ( Col. 8 lines 56-58 The lower electrode 82 may pass through the etch stop layer 75 and contact the upper surface of the landing pad 69 ); a capacitor top electrode (Fig. 2A: upper electrode 86 ) disposed over the capacitor bottom electrode ( Fig. 2A #82 ); and a capacitor dielectric (Fig 2A: capacitor dielectric layer 84 ) disposed between the capacitor bottom electrode ( Fig. 2A #82 ) and the capacitor top electrode ( Fig. 2A #86 ).
Lee does not appear to disclose the capacitor bottom electrode includes a lower portion disposed over the capacitor electrode landing pad and an upper portion disposed over the lower portion.
However, Chiu teaches the capacitor bottom electrode ( Fig. 2B #268 ) includes a lower portion ( Fig. 2B #268b) disposed over the capacitor electrode landing pad ( [0054] The bottom surface of the capacitor structure 216 may be electrically coupled and/or physically coupled with the interconnect structure 214 ) and an upper portion ( Fig. 2B #268a ) disposed over the lower portion ( Fig. 2B #268b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chiu with Kim, Yu, and Lee to implement the capacitor structure comprises: a capacitor bottom electrode disposed over the capacitor electrode landing pad; a capacitor top electrode disposed over the capacitor bottom electrode; and a capacitor dielectric disposed between the capacitor bottom electrode and the capacitor top electrode, wherein the capacitor bottom electrode includes a lower portion disposed over the capacitor electrode landing pad and an upper portion disposed over the lower portion because this approach increases the effective overlap area for higher capacitance.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Yu et al.; US 11,881,507 B2; 07/2022 as it relates to claim 1 above and further in view of Chiu et al.; US 2025/0098187 A1; 09/2023
Claim 10: Kim and Yu disclose the semiconductor device of claim 1 ( as discussed above).
Neither Kim nor Yu appear to disclose the lower portion of the capacitor bottom electrode has a tapered profile.
However, Chiu teaches the lower portion ( Fig. 2B second bottom electrode layer 268b ) of the capacitor bottom electrode ( Fig. 2B bottom electrode 268 ) has a tapered profile ( as shown in Fig. 2B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chiu with Kim, and Yu to implement the lower portion of the capacitor bottom electrode has a tapered profile because this approach stabilizes dielectric and electrode structures during fabrication.
Claims 12-13 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Lee et al.; US 12,696,437 B2; 11/2023
Claim 12: Kim discloses the semiconductor device of claim 11 ( as discussed above).
Kim does not appear to disclose a capacitor electrode landing pad disposed over and covering the conductive plug.
However, Lee teaches a capacitor electrode landing pad ( Fig. 2A #69 ) disposed over and covering ( Col. 8 lines 61-65 The capacitor structure 80 may be electrically connected to the landing pad 69 and the contact plug 60 ) the conductive plug ( Fig. 2A #60 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Kim to implement a capacitor electrode landing pad disposed over and covering the conductive plug because this approach enhances mechanical stability, maximizes contact reliability, increases effective capacitance, and reduces short-circuit risks.
Claim 13: Kim and Lee disclose the semiconductor device of claim 12 ( as discussed above).
Kim teaches the bit line ( Fig. 2C #140 ) is configured to electrically connect one of the doped regions ( Fig. 2C #107 ) to a bit line structure ( as shown in Fig. 2C ).
Claim 14 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Lee et al.; US 12,696,437 B2; 11/2023 as it relates to claim 13 above and further in view of Choi et al.; US 2022/0028860 A1; 03/2021
Claim 14: Kim and Lee disclose the semiconductor device of claim 13 ( as discussed above).
Neither Kim nor Lee appear to disclose the bit line comprises a bit line bottom electrode, a bit line top electrode, a bit line mask pattern, and a bit line spacer.
However, Choi teaches the bit line ( Fig. 3: LST ) comprises a bit line bottom electrode ( Fig. 3: CP ), a bit line top electrode ( Fig. 3: BL ), a bit line mask pattern ( Fig. 3: BP ), and a bit line spacer ( Fig. 3: SP ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Choi with Kim and Lee to implement the bit line comprises a bit line bottom electrode, a bit line top electrode, a bit line mask pattern, and a bit line spacer because this approach enhances electrical performance, fabrication precision, reliability, and scalability.
Claims 15-18 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Lee et al.; US 12,696,437 B2; 11/2023 and Choi et al.; US 2022/0028860 A1; 03/2021 as it relates to claim 14 above and further in view of Huang; US 2021/0074639 A1; 09/2019
Claim 15: Kim, Lee, and Choi disclose the semiconductor device of claim 14 ( as discussed above).
Neither Kim nor Lee nor Choi appear to disclose a bottom surface of the bit line bottom electrode is substantially coplanar with the top surface of the bit line contact; a bottom surface of the bit line top electrode is substantially coplanar with a top surface of the bit line bottom electrode; and a bottom surface of the bit line mask pattern is substantially coplanar with a top surface of the bit line top electrode.
However, Huang teaches a bottom surface of the bit line bottom electrode ( Fig. 1: bit line bottom electrode 507 ) is substantially coplanar with the top surface of the bit line contact ( Fig. 1: bit line contact 505 ); a bottom surface of the bit line top electrode ( Fig. 1: bit line top electrode 509 ) is substantially coplanar with a top surface of the bit line bottom electrode ( Fig. 1 #507 ); and a bottom surface of the bit line mask pattern ( Fig. 1: bit line mask 511 ) is substantially coplanar with a top surface of the bit line top electrode ( Fig. 1 #509 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Kim, Lee, and Choi to implement a bottom surface of the bit line bottom electrode is substantially coplanar with the top surface of the bit line contact; a bottom surface of the bit line top electrode is substantially coplanar with a top surface of the bit line bottom electrode; and a bottom surface of the bit line mask pattern is substantially coplanar with a top surface of the bit line top electrode because this approach influences electrical performance, reliability, and mechanical stability.
Claim 16: Kim, Lee, Choi, and Huang disclose the semiconductor device of claim 15 ( as discussed above).
Neither Kim nor Lee nor Choi appear to disclose a top surface of the bit line spacer is substantially coplanar with a top surface of the bit line mask pattern, and a bottom surface of the bit line spacer is substantially coplanar with a bottom surface of the bit line contact.
However, Huang teaches a top surface of the bit line spacer ( Fig. 1 bit line spacers 513 ) is substantially coplanar with a top surface of the bit line mask pattern ( Fig. 1 bit line mask 511 ), and a bottom surface of the bit line spacer ( Fig. 1 #513 ) is substantially coplanar with a bottom surface of the bit line contact ( Fig. 1 #505 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Kim, Lee, and Choi to implement a top surface of the bit line spacer is substantially coplanar with a top surface of the bit line mask pattern, and a bottom surface of the bit line spacer is substantially coplanar with a bottom surface of the bit line contact because this approach integrates process simplicity, alignment fidelity, electrical uniformity, and device reliability.
Claim 17: Kim, Lee, Choi, and Huang disclose the semiconductor device of claim 16 ( as discussed above).
Neither Kim nor Lee nor Choi appear to disclose sidewalls of the bit line contact, the bit line bottom electrode, the bit line top electrode, the bit line mask pattern, and the bit line spacer are substantially coplanar.
However, Huang teaches sidewalls of the bit line contact ( Fig. 1 #505 ), the bit line bottom electrode ( Fig. 1 #507 ), the bit line top electrode ( Fig. 1 #509 ), the bit line mask pattern ( Fig. 1 #511 ), and the bit line spacer ( Fig. 1 #513 ) are substantially coplanar ( as shown in Fig. 1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Kim, Lee, and Choi to implement sidewalls of the bit line contact, the bit line bottom electrode, the bit line top electrode, the bit line mask pattern, and the bit line spacer are substantially coplanar because this approach ensures electrical robustness, reduces parasitic effects, and compensates for fabrication variability.
Claim 18: Kim, Lee, Choi and Huang disclose the semiconductor device of claim 17 ( as discussed above).
Neither Kim nor Choi nor Huang appear to disclose the capacitor comprises: a capacitor bottom electrode disposed on the capacitor electrode landing pad; a capacitor top electrode disposed over the capacitor bottom electrode; and a capacitor dielectric disposed between the capacitor bottom electrode and the capacitor top electrode, wherein the capacitor bottom electrode includes a lower portion disposed over the capacitor electrode landing pad and an upper portion disposed over the lower portion.
However, Lee teaches the capacitor comprises: a capacitor bottom electrode ( Fig. 2A: lower electrode 82 ) disposed on the capacitor electrode landing pad ( Col. 8 lines 56-58 The lower electrode 82 may pass through the etch stop layer 75 and contact the upper surface of the landing pad 69 ); a capacitor top electrode (Fig. 2A: upper electrode 86 ) disposed over the capacitor bottom electrode ( Fig. 2A #82 ); and a capacitor dielectric (Fig 2A: capacitor dielectric layer 84 ) disposed between the capacitor bottom electrode ( Fig. 2A #82 ) and the capacitor top electrode ( Fig. 2A #86 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Kim, Choi, and Huang to implement the capacitor comprises: a capacitor bottom electrode disposed on the capacitor electrode landing pad; a capacitor top electrode disposed over the capacitor bottom electrode; and a capacitor dielectric disposed between the capacitor bottom electrode and the capacitor top electrode, wherein the capacitor bottom electrode includes a lower portion disposed over the capacitor electrode landing pad and an upper portion disposed over the lower portion because this approach increases the effective overlap area for higher capacitance.
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Lee et al.; US 12,696,437 B2; 11/2023, Choi et al.; US 2022/0028860 A1; 03/2021, and Huang; US 2021/0074639 A1; 09/2019 as it relates to claim 18 above and further in view of Chiu et al.; US 2025/0098187 A1; 09/2023
Claim 19: Kim, Lee, Choi and Huang the semiconductor device of claim 18 ( as discussed above ).
Neither Kim nor Lee nor Choi nor Huang appear to disclose the lower portion of the capacitor bottom electrode has a tapered profile.
However, Chiu teaches the lower portion ( Fig. 2B second bottom electrode layer 268b ) of the capacitor bottom electrode ( Fig. 2B bottom electrode 268 ) has a tapered profile ( as shown in Fig. 2B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chiu with Kim, Lee, Choi, and Huang to implement the lower portion of the capacitor bottom electrode has a tapered profile because this approach stabilizes dielectric and electrode structures during fabrication.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 12,191,364 B2; 03/2022 in view of Lee et al.; US 12,696,437 B2; 11/2023, Choi et al.; US 2022/0028860 A1; 03/2021, Huang; US 2021/0074639 A1; 09/2019, and Chiu et al.; US 2025/0098187 A1; 09/2023 as it relates to claim 19 above and further in view of Oh et al.; US 12,696,749 B2; 05/2023
Claim 20: Kim, Lee, Choi, Huang, and Chiu disclose the semiconductor device of claim 19 ( as discussed above ).
Neither Kim nor Lee nor Choi nor Huang nor Chiu appear to disclose the second part of the conductive plug is formed using an electroplating process.
However, Oh teaches the second part of the conductive plug is formed using an electroplating process ( Col. 14 lines 49 – 52 The operation of filling the conductive plug may include a sputtering process, an operation of forming a seed metal layer, and an operation of performing an electropating process after forming the conductive barrier layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Oh with Kim, Lee, Choi, Huang, and Chiu to implement the second part of the conductive plug is formed using an electroplating process because this approach enables void-free filling, high conductivity, and proper planarization for high aspect ratio contacts in miniaturized semiconductor devices.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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