DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 12/10/2024.
Claims 1-20 are pending. Claims 1, 10, and 16 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Information Disclosure Statement
5. IDS submitted on 12/10/2024 has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KATOCH et al. (US 2019/0392876 A1).
Regarding independent claim 1, KATOCH teaches a memory device (Fig. 1: 100), comprising:
a memory array (Fig. 1: 110 array column with regions) configured to receive a first word line signal (Fig. 1: TSA/ TWA) and a second word line signal (Fig. 1: TSA/ TWA);
a first tracking cell (Fig. 1: 114A) configured to adjust a tracking bit line signal (Fig. 1: TBL) according to (according to conveys a broad functional relationship between components in electronic circuit) the first word line signal (para [0056]: tracking cell activated by tracking word line controls charging and discharging of tracking bit line TBL);
a second tracking cell (Fig. 1: 114B) configured to adjust the tracking bit line signal (Fig. 1: TBL) according to the second word line signal (para [0056]); and
a word line driver (Fig. 1: 130 tracking word line driver) configured to adjust the first word line signal (Fig. 1, Fig. 2: TSA/ TWA, see Fig. 2: TS, TSA) and the second word line signal (Fig. 1, Fig. 2: TSB/ TWB, see Fig. 2: TS, TSB) according to a first distance between the first tracking cell (Fig. 1: TBL node connected to 114A) and a common node (Fig. 1: TBL node connected to 150) and a second distance between the second tracking cell (Fig. 1: TBL node connected to 114B) and the common node (Fig. 1: TBL node connected to 150. See Fig. 2 in context of para [0066], para [0068]: 114B is farther away than 114A from 150 node and accordingly WLB pulse width/ TSB signal delay is longer than WLA pulse width/ TSA signal delay).
Regarding claim 2, KATOCH teaches the memory device of claim 1, wherein when the first word line signal is transmitted to the memory array (Fig. 1: TSA/ TWA is transmitted in 110A region of array),
the first tracking cell (Fig. 1: 114A) is configured to pull a voltage level of the tracking bit line signal (para [0056]: tracking cell charges, discharges TBL).
Regarding claim 3, KATOCH teaches the memory device of claim 1, further comprising: a third tracking cell (e.g., Fig. 1: 114C) configured to emulate the memory array (tracking cells are similar in structure and mimics actual cells), and
pull a voltage level of the tracking bit line signal when the first word line signal is transmitted to the memory array (para [0056]: activated by WL, tracking cell charges, discharges TBL).
Regarding claim 4, KATOCH teaches the memory device of claim 1, wherein in response to a rising edge of the first word line signal, the first tracking cell is configured to pull low a voltage level of the tracking bit line signal, to generate a falling edge of the tracking bit line signal (See Fig. 2 in context of para [0054]-para [0056]: TBLV falling edge in correspondence with TS rising edge).
Regarding claim 5, KATOCH teaches the memory device of claim 1, wherein when the second word line signal is transmitted to the memory array, the second tracking cell is configured to pull a voltage level of the tracking bit line signal (See Fig. 2 in context of para [0054]-para [0056]: 114A, 114B functions in similar fashion with respect to TBL).
Regarding claim 6, KATOCH teaches the memory device of claim 1, wherein in response to a distance between the second tracking cell and the common node greater than a distance between the first tracking cell and the common node (Fig. 2), an edge of the second word line signal is slower than an edge of the first word line signal (See Fig. 2, para [0076]: TSA, WLA signal vs. TSB, WLB signal falling edge).
Regarding claim 7, KATOCH teaches the memory device of claim 6, wherein the edge of the second word line signal and the edge of the first word line signal are falling edges (See Fig. 2 in context of para [0076])
Regarding claim 8, KATOCH teaches the memory device of claim 1, wherein the first tracking cell comprises a first switch, a first terminal of the first switch is configured to receive the tracking bit line signal (para [0026]: tracking cell employed with SRAM 6T cell. D/S of access transistor of 6T SRAM tracking cell is configured for this connection), and
a control terminal of the first switch is configured to receive the first word line signal (para [0026]: tracking cell employed with SRAM 6T cell. Gate of access transistor of 6T SRAM tracking cell is configured for this connection).
Regarding claim 9, KATOCH teaches the memory device of claim 8, wherein the second tracking cell comprises a second switch, a first terminal of the second switch is configured to receive the tracking bit line signal, a control terminal of the second switch is configured to receive the second word line signal, (para [0026]: tracking cell employed with SRAM 6T cell. See claim 8 rejection analysis)
and each of a second terminal of the first switch and a second terminal of the second switch is coupled to a ground (Coupling to Vss meets this limitation. See Fig. 2 and Fig. 1).
Regarding independent claim 10, KATOCH teaches a memory device (Fig. 1: 100 memory circuit, para [0015]), comprising:
a memory array (see Fig. 1: 110 array column with regions) configured to receive a first word line signal (Fig. 1, Fig. 2: TSA/ TWA) and a second word line signal (Fig. 1, Fig. 2: TSB/ TWB) different from each other;
a first tracking cell (Fig. 1: 114A) configured to emulate the memory array (para [0013], para [0014]);
a tracking bit line (Fig. 1: TBL tracking bitline) configured to transmit a tracking bit line signal to the first tracking cell (Fig. 1: 114A, see para [0046], para [0048]);
a first switch (Fig. 1: 130A “tracking word line driver”, see Fig. 4: 400 structure) coupled to the tracking bit line (Fig. 4: coupled via CPK timing signal input connected to TBL) and configured to receive the first word line signal (receive Fig. 4 inputs to get output Fig. 4: TS, TWL out. See Fig. 1: TSA, TWLA); and
a second switch (Fig. 1: 130B “tracking word line driver”, see Fig. 4: 400 structure) coupled to the tracking bit line (Fig. 4: coupled via CPK timing signal input connected to TBL) and configured to receive the second word line signal (receive Fig. 4 inputs to get output Fig. 4: TS, TWL out. See Fig. 1: TSB, TWLB).
Regarding claim 11, KATOCH teaches the memory device of claim 10, wherein a control terminal (taken as driver input terminal) of the first switch is configured to receive the first word line signal (Fig. 1: input of 130A “tracking word line driver” receives TS/ TW)
Regarding claim 12, KATOCH teaches the memory device of claim 11, wherein a control terminal of the second switch is configured to receive the second word line signal (see claim 11 analysis).
Regarding claim 13, KATOCH teaches the memory device of claim 10, further comprising: a tracking circuit configured to generate the tracking bit line signal based on a first distance between a first node and a common node and a second distance between a second node and the common node (Fig. 2 in context of para [0051]-para [0053], para [0056]), wherein the first switch and the second switch are coupled to a first node and a second node (Fig. 2: 114A, 114B nodes connected to TBL. See para [0051]-para [0053], para [0056]), respectively.
Regarding claim 14, KATOCH teaches the memory device of claim 13, wherein a first terminal of the second switch is coupled to the tracking bit line at the second node, and each of a second terminal of the first switch and a second terminal of the second switch is coupled to a ground (Fig. 1 and Fig. 2: circuitry and components are operably coupled in electronics functionality and according to claimed limitations).
Regarding claim 15, KATOCH teaches the memory device of claim 13, wherein in response to the second distance larger than the first distance, an edge of the second word line signal is slower than a falling edge of the first word line signal (See Fig. 2: TSA/ TWA vs. TSB/TWB).
Regarding independent claim 16, KATOCH teaches a method (see Abstract: operation method of Fig. 1: 100 memory circuit), comprising:
modulating a first word line signal (modulating pulse width of word line pulse signal. See Fig. 1, Fig. 2: WLA) by a control circuit (Fig. 1: 150 tracking circuit) coupled to a common node (Fig. 1: TBL node connected to 150);
charging a tracking word line (Fig. 1: TWLA/ TSA) by the control circuit (Fig. 1: 150) to generate a tracking word line signal (Fig. 1: TWLA. See para [0048]-para [0049]);
turning on a first latch circuit (Fig. 1: 150 circuitry and 160 circuitry combined, see para [0048]) to pull down a voltage level (para [0048]: Vss) of a tracking bit line signal (Fig. 1: TBL) based on a resistance between a first node (Fig. 1: TBL connecting node to 114A) and the common node (Fig. 1: TBL connecting node to 150); and
turning on each of a first switch (Fig. 1: 130) and a second switch (Fig. 1: switches inside 150) by the first word line signal (see Fig. 2),
wherein the tracking bit line signal (Fig. 1: TBL) is transmitted by a tracking bit line (tracking bit line, see Fig. 1: TBL),
the first latch circuit (Fig. 1: 150 circuitry and 160 circuitry combined) is coupled to the first node (Fig. 1: coupled to 112A cell),
the first switch (Fig. 1: 130) is coupled between a data line (Fig. 1: input/ output lines from 114) and the first latch circuit (Fig. 1: 150 circuitry and 160 circuitry combined), and
the second switch (Fig. 1: switches inside 150) is coupled between the tracking bit line (Fig. 1: TBL) and the first latch circuit (Fig. 1: 150 circuitry and 160 circuitry combined).
Double Patenting
9. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
10a. Claims 1, 10, and 16 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,211,587 B2. Although the claims at issue are not identical, they are not patentably distinct from each other – see analysis in the following:
Regarding claim 1, US 12,211,587 B2 teaches a memory device (US 12,211,587 B2: claims 1-7), comprising:
a memory array configured to receive a first word line signal and a second word line signal; (US 12,211,587 B2: claim 1)
a first tracking cell configured to adjust a tracking bit line signal according to the first word line signal; (US 12,211,587 B2: claim 1, lines 4-9)
a second tracking cell configured to adjust the tracking bit line signal according to the second word line signal; and (US 12,211,587 B2: claim 1, lines 4-9)
a word line driver configured to adjust the first word line signal and the second word line signal according to a first distance between the first tracking cell and a common node and a second distance between the second tracking cell and the common node. (US 12,211,587 B2: claim 1, lines 10-16, see also claims 2-7)
Regarding claim 10, US 12,211,587 B2 teaches a memory device (US 12,211,587 B2: claims 8-13), comprising:
a memory array configured to receive a first word line signal and a second word line signal different from each other; (US 12,211,587 B2: claim 8)
a first tracking cell configured to emulate the memory array; a tracking bit line configured to transmit a tracking bit line signal to the first tracking cell; (US 12,211,587 B2: claim 8, lines 3-5)
a first switch coupled to the tracking bit line and configured to receive the first word line signal; and a second switch coupled to the tracking bit line and configured to receive the second word line signal. (US 12,211,587 B2: claim 8, line 6-14)
Regarding claim 16, US 12,211,587 B2 teaches a method (US 12,211,587 B2: claims 14-20), comprising:
modulating a first word line signal by a control circuit coupled to a common node; charging a tracking word line by the control circuit to generate a tracking word line signal; (US 12,211,587 B2: claim 14, line 1-3. See also claims 14-20)
turning on a first latch circuit to pull down a voltage level of a tracking bit line signal based on a resistance between a first node and the common node; and (US 12,211,587 B2: claim 14, lines 8-15)
turning on each of a first switch and a second switch by the first word line signal, wherein the tracking bit line signal is transmitted by a tracking bit line, the first latch circuit is coupled to the first node, the first switch is coupled between a data line and the first latch circuit, and the second switch is coupled between the tracking bit line and the first latch circuit. (US 12,211,587 B2: claims 15-16. See also claims 14-120)
10b. Claims 1, 10, and 16 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,727,972 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Similar analysis can be performed as above. Analysis with exact limitation matching is not shown but major similarity is described in the following:
US 11,727,972 B2 teaches a memory device (US 11,727,972 B2: claims 1-8: memory device), comprising: a first memory cell configured to receive a first word line signal (US 11,727,972 B2: claim 1, lines 1-3: memory cells); a first tracking cell configured to emulate the first memory cell (US 11,727,972 B2: claim 1, lines 4-5: first plurality of tracking cells. Tracking cells emulate memory cells); a tracking bit line configured to transmit a tracking bit line signal to the first tracking cell (US 11,727,972 B2: claim 1, lines 4-5: tracking bit line coupled to a first plurality of tracking cells); a second tracking cell configured to adjust the tracking bit line signal according to the first word line signal (US 11,727,972 B2: claim 1, lines 19-22); and a word line driver configured to adjust the first word line signal according to the tracking bit line signal (US 11,727,972 B2: claim 1, lines 8-15) and a first distance between the second tracking cell and a common node on the tracking bit line (US 11,727,972 B2: claim 1, lines 8-15: Correlated resistance of a length of the tracking bit line is used. See also claim 6 and claim 8 for common node).
US 11,727,972 B2 teaches a memory device (US 11,727,972 B2: claims 1-8: memory device), comprising: a first memory cell configured to receive a first word line signal (US 11,727,972 B2: claim 1, lines 1-3: memory cells); a first tracking cell configured to emulate the first memory cell (US 11,727,972 B2: claim 1, lines 4-5: first plurality of tracking cells. Tracking cells emulate memory cells); a tracking bit line configured to transmit a tracking bit line signal to the first tracking cell (US 11,727,972 B2: claim 1, lines 4-5: tracking bit line coupled to a first plurality of tracking cells); a first switch coupled to the tracking bit line at a first node and configured to receive the first word line signal (US 11,727,972 B2: claim 4: pull-down transistors); and a tracking circuit configured to generate the tracking bit line signal based on a first distance between the first node and a common node on the tracking bit line (US 11,727,972 B2: Claim 8: tracking circuit and Claim 1).
US 11,727,972 B2 teaches a method (US 11,727,972 B2: claims 17-20: method, see also claims 1-16), comprising: modulating a first word line signal by a control circuit coupled to a common node (US 11,727,972 B2: claim 17, lines 1-7); receiving the first word line signal by a first memory cell (US 11,727,972 B2: claim 17, claims 1-8); emulating the first memory cell by a first tracking cell (US 11,727,972 B2: claim 17, claims 1-8); transmitting a tracking bit line signal to the first tracking cell (US 11,727,972 B2: claim 17, claims 1-8); and turning on a latch circuit to pull down a voltage level of the tracking bit line signal based on a resistance between a first node and the common node, wherein the latch circuit is coupled to the first node (US 11,727,972 B2: claims 9, 11, and 17).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Cheng (US 2013/0194860 A1) is applicable for all claims. Cheng teaches a memory device (Fig. 3: 300 memory device), comprising: a first memory cell (Fig. 3: 304) configured to receive a first word line signal (abstract, para [0011]: “wordline pulse”); a first tracking cell (Fig. 3: 314 “write tracking cells”) configured to emulate the first memory cell (Fig. 3: 304 “memory cells”); a tracking bit line (Fig. 3: BLTRK) configured to transmit a tracking bit line signal (Fig. 3: TRKOUT) to the first tracking cell (abstract, para [0011]); a second tracking cell (Fig. 3: 316 “dummy tracking cell”) configured to adjust the tracking bit line signal (Fig. 3: TRKOUT) according to the first word line signal (“wordline pulse”); and a word line driver (e.g. Fig. 3: wordline Driver 1) configured to adjust the first word line signal (abstract, para [0011]: “wordline pulse”) according to the tracking bit line signal (Fig. 3: TRKOUT) and a first distance between the second tracking cell and a common node on the tracking bit line (para [0019], para [0011], abstract). Hsu et al. (US 2018/0151219 A1) is applicable for all claims. Hsu teaches a memory device (Fig. 1: 100 “memory device”, see Fig. 1-Fig. 4 for illustrated components and functionality. HSU (US 9,111,595 B2): Fig. 1-Fig. 6 disclosure applicable for all claims. HSU teaches A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal. Li (US 20220130344 A1): Fig. 1-Fig. 7C applicable for claims.
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further, any double patenting rejection must be over-come.
Regarding claims above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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