DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 2-21 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 2-3, 5, 11, 14 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vogt (US 2004/0246786).
Claim 2, Vogt (Fig. 3-6) clearly shows a plurality of memory module (DRAM 58 modules), each module has a plurality of integrated DRAM chips (or array) in same module (see Fig. 6), and Fig. 6 also shows each DRAM module 58 has two side ports (on left & right sides) for transferring data between different but adjacent DRAM modules and host/CPU, and that a common data path (or bus 54 & 56) is shown coupled to the first port (on left side) of each respective DRAM module and also coupled to its second port (on right side) so that any data can be forwarded (back & forth) from the host 50 to the first port and also forwarding to the second port (on right side) based on the control signal (from CLK buffer 78) as claimed. Note that the common data path (54) has 2 lines and is split by the first DRAM module into a first set of data lines (54 on left side of each module) and a second set of data lines (54 on right side of each module) as well.
Claim 3, the CLK buffer is a type of “register” for holding a clock signal (CLK) as controlling pulse for activating the data transfer between multiple/parallel DRAM modules as see in Fig. 6.
Claim 5 & 14, the first set of data lines 54 (on left side of the first DRAM module) is use to receive data from the external host/CPU 50, and the second set of data lines 54 (on right side of the first module) is used to transmit data from the first module 58 to the second/adjacent module 58 is seen in Fig. 6.
Claim 11, Figs. 1 & 6 show DRAM configurations wherein each DRAM module can have multiple DRAM chips stacked upon each other to minimize space, and thus the configuration of stacked dies are considered as optional design choices and//or well-known knowledge to a skilled person in this art as well.
Claim 20, Fig. 3 shows the memory controller 50 coupled to all these cascaded DRAM modules by the common bus (54 & 56), and this is considered a conventional knowledge that the controller 50 uses both address & data to select and access to each/particular module (in the cascaded chain) as also well-known in this art. See Fig. 6 below:
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Second port)][AltContent: textbox (First port)]
[AltContent: arrow][AltContent: arrow][AltContent: textbox (First & second data lines 54/56)]
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3. Claims 2, 5, 11, 14 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mooney et al (US 2005/0146980).
Claim 2, Mooney (Fig. 6-8) clearly shows a plurality of memory module (DRAM modules 1-4, see Fig. 8), each module can store a plurality of integrated DRAM chips (or array M11 to M44, etc.), and Fig. 6 also shows each DRAM module 58 has two side ports (on left & right sides) for transferring data between adjacent DRAM modules and host/cpu, and that a common data path (see left & right arrows) is shown coupled to the first port (on left side) of each respective DRAM module and also coupled to its second port (on right side) so that any data can be forwarded (back & forth) from the host/controller to the first port and also forwarding to the second port (on right side) based on the control signals (or data strobes & clock signals, etc.) as claimed. Note that the common data path has 2 lines and is split by the first DRAM module into a first set of data lines (see lines 58 on left side of each module) and a second set of data lines (see lines 70-on right side of each module) as well.
Claim 5 & 14, the first set of data lines 50/56 (on left side of the first DRAM module) is use to receive data from the external host/CPU, if any, and the second set of data lines 70/76 (on right side of the first module) is used to transmit data from the first module (see Module 1, Fig. 8 as example) to the second/adjacent module (or Module 2) as shown in Fig. 8.
Claim 11, Figs. 8-9 show DRAM configurations wherein each DRAM module can have multiple DRAM chips stacked upon each other to minimize space, and thus the configuration of stacked dies are considered as optional design choices and//or well-known knowledge to a skilled person in this art as well.
Claim 20, Figs. 6-9 shows that the memory controller is coupled to all these cascaded DRAM modules by the common bus between them, and this is considered a conventional knowledge that the controller uses both address & data to select and access to each/particular module (in the cascaded chain) as also well-known in this art..
See Fig. 8 illustration below:
[AltContent: textbox (First & second data lines
= 50/56 & 70/76)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Second port)][AltContent: textbox (First port)]
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4. Claims 2, 5, 14 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ross (US 2020/0097207).
Claim 2, Ross (Fig. 2) clearly shows a plurality of memory module (stacked DRAM 221-1 to 221-15 cell device), each device has its own cell array with two side data ports (see 222-1 & 222-2 as example), and Fig. 2 further shows each DRAM device 221 as two side ports (on left & right sides) for transferring data between DRAM devices and controllers, and that a common data path (or bus 212 & 213) is shown coupled to the first port (on left side) of each respective DRAM device and also coupled to its second port (on right side) so that any data can be forwarded (back & forth) from the host 202 to the first port and also forwarding to the second port (on right side) based on the control signal (from controller/host) as claimed. For example, Fig. 2shows the common data path has 2 sets of data lines and is split by the first DRAM device (221-1) into a first set of data lines (212-1) on left side and a second set of data lines (213-1) on right side of device 221-1) as seen.
Claim 5 & 14, the first set of data lines 212 (on left side of each DRAM device) is use to receive data from the external host/CPU 202, and the second set of data lines 213 (see right side of the first device 221-1) is used to transmit data from the first device 221-1 to the second/below device 221-3 is seen in Fig. 6.
Claim 20, Fig. 3 shows the memory controller coupled to all these cascaded DRAM modules by the two-way, common bus between them, and this is considered a conventional knowledge that the controller uses both address & data to select and access to each/particular module (in the cascaded chain) as also well-known in this art.
Allowable Subject Matter
5. The remaining claims 4, 6-10, 12-13, 15-19 & 21 are objected as being depend upon their respective rejected/parent claims above, but they tentatively contain additional/allowable subject matter over the prior arts, which are not seen elsewhere at this time.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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