Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-3 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. Patent Application 8,514,605) in view of Li (U.S. Patent Application 9,461,094).
Claim 1. An integrated chip, comprising: a memory device, the memory device having a data storage structure between a first electrode and a second electrode (data-storage structure between fist and second electrodes, Chen Fig 1-2, corresponding to electrodes 15,16 and layers 12-14); a first unidirectional current controller (first diode 32, Chen Fig 4); a second unidirectional current controller (second diode 34, Chen Fig 4); and a conductor arranged between the first unidirectional current controller and the data storage structure along a first conductive path and further arranged between the second unidirectional current controller and the data storage structure along a second conductive path (opposing forward-bias direction currents I1 and I2 corresponding to 32 and 34 respectively, Chen Fig 4), wherein a part of the first conductive path overlaps a part, but not all, of the second conductive path (parallel diode branches, Chen Fig 4), but does not disclose disposed within ILD structure over substrate.
Li discloses forming an MTJ and a bidirectional diode selector in a semiconductor integrated circuit having BEOL interconnects and deposited interlayer dielectric materials (MTJ and bidirectional diode selector, Li Fig 4-7) for the purpose of identifying the reduction of selector or access device cell area and improve MRAM density.
Since Li and Chen are both from the same field of endeavor (accessing MTJ memory cells), the purpose disclosed by Li would have been recognized in the pertinent art of Chen.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the MTJ circuit taught by Chen using the substrate implementation as taught by Li for the purposes of identifying the reduction of selector or access device cell area and improve MRAM density.
Claim 2. Chen and Li teach the integrated chip of claim 1, wherein the first unidirectional current controller and the second unidirectional current controller are a same type of unipolar selector (Diodes 32 and 34 same type of unidirectional selector Chen Fig. 4).
Claim 3. Chen and Li teach the integrated chip of claim 1, wherein the first unidirectional current controller and the second unidirectional current controller are different types of unipolar selectors (Not a critical limitation since claim 2 claims the opposite. Diodes types 32 and 34 type of unidirectional selector Chen Fig. 4).
Claim 7. The integrated chip of claim 1, wherein the conductor comprises a conductive layer arranged between the first unidirectional current controller and the memory device (conductive layer between the controllers and MTJ, Chen Fig 4), the conductive layer having a width that is substantially equal to a width of the first unidirectional current controller (as seen in Chen Li 4).
Claim 8. The integrated chip of claim 1, wherein the first unidirectional current controller is oriented to allow current to flow toward the memory device and the second unidirectional current controller is oriented to allow current to flow away from the memory device (as seen in Chen Fig 4).
Claim 9. The integrated chip of claim 1, wherein the first unidirectional current controller comprises a protrusion extending outward from a lower surface of the first unidirectional current controller (as seen in Li Fig 4).
Claim 10. Chen discloses an integrated chip, comprising: one or more conductive interconnects arranged within a lower dielectric structure, a memory device disposed within an upper dielectric structure, wherein the memory device comprises a data storage structure arranged between a first electrode and a second electrode (data-storage structure between fist and second electrodes, Chen Fig 1-2, corresponding to electrodes 15,16 and layers 12-14); a first monodirectional current selector disposed within the upper dielectric structure and electrically coupled to the first electrode (first diode 32, Chen Fig 4); and a second monodirectional current selector disposed within the upper dielectric structure and electrically coupled to the first electrode (second diode 34, Chen Fig 4), but does not disclose disposed within ILD structure over substrate.
Li discloses forming an MTJ and a bidirectional diode selector in a semiconductor integrated circuit having BEOL interconnects and deposited interlayer dielectric materials (MTJ and bidirectional diode selector, Li Fig 4-7) for the purpose of identifying the reduction of selector or access device cell area and improve MRAM density.
Since Li and Chen are both from the same field of endeavor (accessing MTJ memory cells), the purpose disclosed by Li would have been recognized in the pertinent art of Chen.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the MTJ circuit taught by Chen using the substrate implementation as taught by Li for the purposes of identifying the reduction of selector or access device cell area and improve MRAM density.
Claim 11. The integrated chip of claim 10, wherein the first monodirectional current selector and the second monodirectional current selector respectively comprise one or more of a diode, a filament based selector, a rectifier, a varistor-type selector, an ovonic threshold switch (OTS), a doped-chalcogenide-based selector, a Mott effect based selector, a mixed-ionic-electronic-conductive (MIEC)-based selector, and a field-assisted-superliner-threshold (FAST) selector (diodes taught in Chen Fig 4).
Claim 12. The integrated chip of claim 10, wherein the first monodirectional current selector and the second monodirectional current selector are disposed along a horizontal plane that is parallel to an upper surface of the substrate (In a parallel plane as seen in Chen Fig 4).
Claim 13. The integrated chip of claim 10, wherein the first monodirectional current selector extends from directly below the memory device to laterally outside of the memory device (as seen in Chen Fig 4).
Claim 14. The integrated chip of claim 10, further comprising: an interconnect via laterally separated from the first monodirectional current selector by the upper dielectric structure, wherein the interconnect via vertically extends past a top of the first monodirectional current selector (separate via from current selector taught in Li Fig 12).
Claim 15. The integrated chip of claim 10, wherein the first monodirectional current selector and the second monodirectional current selector respectively have an area that is approximately equal to 1 to 5 times an area of the memory device (as seen in Li Fig 12).
Claim 16. The integrated chip of claim 10, wherein the first monodirectional current selector and the second monodirectional current selector are connected to the memory device along conductive paths that share a same conductive structure (selectors connected to the MTJ through a shared conductive connection, Chen Fig 4).
Claim 17. The integrated chip of claim 10, wherein the first monodirectional current selector comprises a layer of diode metal and a layer of semiconductor material over the layer of diode metal, the layer of diode metal having a bottommost surface that is narrower than a top surface of the layer of diode metal (as seen in Li Fig 12).
Claim 18. A method of forming an integrated chip, comprising: forming a first unipolar selector; forming a memory device over the upper surface of the semiconductor substrate after forming the first unipolar selector, the memory device having a data storage structure disposed between a first electrode and a second electrode, wherein the first unipolar selector is electrically coupled to the first electrode; and forming a second unipolar selector over the upper surface of the semiconductor substrate after forming the memory device, wherein the second unipolar selector is configured to be electrically coupled to the first electrode (Chen discloses the MTJ and opposing diode selections Chen Fig 1-4).
Li discloses forming an MTJ and a bidirectional diode selector in a semiconductor integrated circuit having BEOL interconnects over semiconductor substrate (MTJ and bidirectional diode selector, Li Fig 4-7) for the purpose of identifying the reduction of selector or access device cell area and improve MRAM density.
Since Li and Chen are both from the same field of endeavor (accessing MTJ memory cells), the purpose disclosed by Li would have been recognized in the pertinent art of Chen.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the MTJ circuit taught by Chen using the substrate implementation as taught by Li for the purposes of identifying the reduction of selector or access device cell area and improve MRAM density.
Claim 19. The method of claim 18, wherein forming the first unipolar selector comprises: depositing a diode metal; depositing a semiconductor material onto the diode metal; and etching the diode metal and the semiconductor material to form the first unipolar selector (metal layers and deposit layers are taught in Li Fig 12).
Claim 20. The method of claim 18, wherein the first unipolar selector and the second unipolar selector respectively are a diode, a filament based selector, a rectifier, a varistor-type selector, an ovonic threshold switch (OTS), a doped-chalcogenide-based selector, a Mott effect based selector, a mixed-ionic-electronic-conductive (MIEC)-based selector, or a field-assisted-superliner-threshold (FAST) selector (diodes taught in Chen Fig 4).
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4-6. Wherein the conductor comprises an interconnect wire arranged between the first unidirectional current controller and the memory device, the interconnect wire laterally extending past one or more outermost sidewalls of the first unidirectional current controller, in combination with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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