DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-2, 4-6, 13-15 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith et al (US 6,525,955).
Claims 1, 13 & 17-18, Smith (Fig. 4) shows an programmable fuse comprising a thin oxide layer, configured to be programmed by an applied voltage to a program gate 408, and Fig. 5 shows that a first fuse element 502 coupled to a first transistor (out of two FET 506), wherein the first fuse element 502 is configured to be blown upon application of a first voltage to the first transistor 506, and the first transistor and the first fuse element are connected to a common node, and such common node is also connected to a sense amplifier circuitry 504 as claimed. See below:
[AltContent: arrow][AltContent: textbox (Fuse = 502,
Transistor = 506
Sense amplifier = 504)]
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416
706
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Claim 4, a program path is seen above running from the program transistor 506 to the fuse 502 to ground terminal as claimed.
Claim 6, the prior usage of “poly fuse” or “metal use’ has been well-known in this art. See the background/summary discussion of Smith.
Claims 2, 5 & 14-15 the usage of a similar/second program fuse (with second program path by a second transistor 506) is also considered as conventional practice because a cell array made up from many programmable cells, and each fuse requires a separate program transistor as well as a separate selection/control signal as well) as inherently well-known to a skilled person in this art.
3. Claims 1-2, 4-6, 13-15 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kushiyama (US 7,538,369).
Claims 1, 13 & 17-18, Kushiyama (Fig. 1-2) shows an programmable fuse comprising a metal/poly as programmable resistance (silicide 5), configured to be programmed by an applied voltage to a program gate of transistor 6, and Fig. 5 further shows that such fuse element 5 coupled to a first transistor 6, wherein the first fuse element 5 is configured to be blown upon application of a first voltage to the first transistor 6 and read out path by another transistor 7, and the first transistor and the first fuse element are connected to a common node (= FUSENODE), and such common node is also connected to a sense amplifier circuitry 18 as claimed. See below:
[AltContent: arrow][AltContent: textbox (First Fuse = 5,
First Transistor = 6
Sense amplifier = 18)]
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446
648
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Claim 4, a program path is seen above running from the program transistor 56 to the fuse 5 between ground/GDN and program/VRGM terminal as claimed.
Claim 6, the prior usage of “poly fuse” or “metal use’ has been well-known in this art. See the background/summary discussion of this patent.
Claims 2, 5 & 14-15 the usage of a similar/second program fuse (with second program path by a second transistor 506) is also considered as conventional practice because a cell array made up from many programmable cells, and each fuse requires a separate program transistor as well as a separate selection/control signal as well) as inherently well-known to a skilled person in this art.
4. Claims 1-6, 13-15 & 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hojo et al (US 7,830,736).
Claims 1-6, 13-15 & 17-20, Hojo (Fig. 1-2) shows a first programmable fuse (R1) configured to be programmed by an applied voltage to a program gate of a first transistor 1st/PE, with first fuse R1, to be programed by first transistor; and second fuse R2 be programmed by second transistor 2nd/PE, and each fuse has its own program path as claimed. Fig. 1 further shows a first read out path by first fuse couples to the first transistor, and also a second read path by second fuse couples to the second transistor as claimed. and the first transistor and the first fuse element are connected to a first common node, and this common node also coupled to the sense terminal of sense amplifier SA. Similarly, a second terminal of sense amplifier is also couples to a second common node between the second fuse and second transistor as well.
[AltContent: arrow][AltContent: textbox (First Fuse = R1, First Transistor = N1
Second Fuse = R2, second transistor = N2
Sense amplifier = 15)]
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678
592
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Claim 4, a program path is seen above running from the program transistor N1/N2 to the fuses R1/R2, respectively, and each current path runs between ground/GDN and program/VPB terminal as claimed.
Claim 6, the prior usage of “poly fuse” or “metal use’ has been well-known in this art. See the background/summary discussion of this patent.
Allowable Subject Matter
5. The remaining claims 7-12 & 16 are objected as being dependent upon their respective parent/rejected claims above, but they tentatively contain additional novel limitations to the recited structure above, which are neither suggested by the prior arts nor seen elsewhere at this time.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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