DETAILED ACTION
This action is responsive to the Response to Restriction filed August 19, 2026. Claims 1-20 are pending. Claims 1 and 11 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 1-10) in the reply filed on August 19, 2026, is acknowledged. Applicant did not indicate their election as “with traverse” or “without traverse”. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 19, 2026.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on December 19, 2024, and October 20, 2025. These IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory Device with Segmented Data Lines for Normal and Error Correction Data.
Claim Objections
Claim 9 is objected to because of the following informalities:
The claim recites “a seventh bit (B0e4B) of ECC data.” (emphasis added). The parenthetical appears to be a leftover drawing reference text or is intended to identify a particular bit, but does not appear to be part of the claim limitations. It should be deleted or applicant should explain what it is meant to identify. See 37 CFR 1.75 and MPEP § 608.01(m).
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,499,931. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are broader and generic versions of the claims of the '931 patent anticipated by the reference claims as illustrated below.
Independent claim 1 is met by claim 1 of U.S. Patent No. 12,499,931 as follows:
Instant claim 1
’931 claim 1
NDSP Rational
A memory device
“A memory device, comprising:”
Same statutory class and preamble. No distinction.
a first bit line set, comprising a first bit line and a second bit line
“a plurality of sets of bitlines, comprising a first set of bitlines and a second set of bitlines,” the first set including a first bitline and a second bitline that the CSC couples
Instant first set is the ’931 first set. The extra second set in ’931 is species structure not required by the instant claim and does not distinguish the genus.
a first column selection circuit, coupled to the first bit line and the second bit line
“a column selection circuit, configured to selectively couple … a first bitline in the first set of bitlines … and … a second bitline in the first set of bitlines …”
Same CSC body coupled to both bit lines of that set. No distinction.
a first data line, comprising a first line segment coupled to the first column selection circuit
“a first data line … comprises a first line segment and a second line segment adjacent to each other”; CSC couples “a first bitline in the first set of bitlines … to the first line segment … of the first data line”
Instant first line / first segment is ’931 first data line / first line segment. Instant does not require ’931’s extra adjacent segment; omitting a species limitation does not create a patentable distinction.
a second data line, comprising a second line segment coupled to the first column selection circuit
“a second data line comprises a first line segment”; CSC couples “a second bitline in the first set of bitlines … to the first line segment of the second data line”
Instant “second line segment” is ’931 first line segment of the second data line. Naming difference only.
the first CSC is configured to electrically connect the first BL to the first line segment for transmitting a first bit of normal data
CSC “selectively couple a first bitline in the first set … to the first line segment … of the first data line.” Claim 4 of ’931: that coupling is “to transmit a predetermined data bit.”
Apparatus claim. “Normal data” is the use of the already-claimed bit on that path. Intended use does not patentably distinguish.
and to electrically connect the second BL to the second line segment for transmitting a first bit of Error Correction/Detection data
CSC “selectively couple a second bitline in the first set of bitlines … to the first line segment of the second data line.”
Same two-path CSC. Calling the second path “Error Correction/Detection data” is intended use / an obvious assignment of one of two already-claimed segments. Not a structural distinction.
Instant claim 1 is a genus of ’931 claim 1. The issued claim’s extra set, extra adjacent segment, “separated from each other,” and orthogonal-direction limitations are additional species structure. They do not make the broader instant claim patentably distinct.
The dependent claims do not add a patentable distinction: ’931 1 (base species) and 13 (two groups / three-plus-two segments / orthogonal). Claims 2–4 of ’931 supply the extra-segment and extra-set species.
Instant
Closest ’931 claim(s)
NDSP Rational
2 — first and second vias on the two segments; controller receives the normal bit and the ECC bit in a normal-data read and an ECC-data read
Claim 1 (two segments / two paths). Vias and a controller are not in the ’931 claims.
Conventional I/O taps and a DRAM controller on the two already-claimed paths. Obvious variant of the patented device. Intended-use “two operations” does not distinguish the apparatus.
3 — controller performs the ECC read after the normal read
Claim 1 + claim 2 of instant
Sequence of two reads is a method limitation on an apparatus claim and an obvious order of using the two paths. Not a structural distinction.
4 — third segment on the first data line; second BL set; second CSC ties third BL → third segment (second ECC bit) and fourth BL → second segment (third ECC bit)
Claim 1 (second set of bitlines; first data line has a first and a second adjacent segment; CSC couples a BL of the second set to the second segment of the first data line and a BL of each set to the second data line). Claim 13 (second bitline group coupled to the second and third segments of the first data line and to a second segment of the second data line). Claim 4 (second set selected onto the second segment of the first data line).
Instant claim 4 is the ’931 two-set / extra-segment species with the second path labeled ECC. Same architecture. ECC label is intended use.
5 — third via on the third segment; controller takes the extra ECC bits on the second and third vias
Claim 4 of instant + ’931 claims 1 / 13
Same obvious via + controller add-on as claim 2, applied to the extra segment already in ’931 claims 1 / 13.
6 — first and third segments separated by a first gap
Claim 1: “each data line being segmented into a plurality of line segments separated from each other.” Claim 13: first data line segmented into a plurality of line segments separated from each other, including a third segment.
Instant “gap” is ’931 “separated from each other.” Same limitation.
7 — fourth segment on the second data line; third BL set / third CSC (second normal bit onto first segment, third normal bit onto fourth segment); second gap; first and second gaps form a straight line perpendicular to both data lines
Claim 1: segments of the first data line arranged along a first direction; first and second data lines spaced apart along a second direction orthogonal to the first. Claim 2: different number of segments on the two lines. Claim 3: each line more than two segments. Claim 13: first line has three segments, second line has two, both along the first direction, lines spaced on the orthogonal second direction.
Collinear separated segments on two parallel data lines with an orthogonal spacing are aligned gaps on a line perpendicular to both data lines. Instant claim 7 is that layout plus a third set tiled the same way as ’931 claim 13. Not distinct.
8 — fifth and sixth segments; fourth BL set / fourth CSC; third and fourth gaps forming a second perpendicular straight line
Claims 3 and 13 (more than two segments per line; two groups already mapped onto first/second/third segments of line 1 and first/second of line 2). Repeat of the claim 7 pattern.
Obvious to replicate the same separated-segment / extra-set tile one more time. Second gap-line is the next break in the same first-direction segmentation already claimed in ’931.
9 — fifth BL set / fifth CSC tapping the third and sixth segments (more ECC bits)
Claims 13–14 (further sets in each group selectively coupled to the same segments).
Another set in the same coupling pattern. ECC label still intended use. “(B0e4B)” is an informality, not a distinction.
10 — fourth and fifth vias; controller receives the sixth and seventh ECC bits
Instant 2 / 5 + ’931 13
Same obvious via + controller add-on. No new structure.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, the claim recites: “wherein the memory controller performs the ECC data reading operation after the normal data reading operation.”
Claim 1, as limited by claim 2, is directed to a memory device (an apparatus). Claim 2 recites a memory controller arranged to electrically couple to the first and second vias for receiving bits during a normal data reading operation and an ECC data reading operation. That language is functional capability language in an apparatus claim.
Claim 3 does not further limit the structure or the configured capability of the controller. It recites that the controller performs one reading operation after the other — a method of using the apparatus. A single claim that claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) (see MPEP § 2173.05(p)(II)). It is unclear whether infringement occurs when the memory device is made or sold with a controller capable of the recited sequence, or only when the controller actually performs the ECC data reading operation after the normal data reading operation.
Applicant may overcome this rejection by amending claim 3 to apparatus/capability form consistent with claim 2, for example: “wherein the memory controller is arranged to perform the ECC data reading operation after the normal data reading operation.”
Regarding claim 10, the claim recites “a fourth via, arranged to electrically couple to the third line segment” and “a fifth via, arranged to electrically couple to the sixth line segment.”
Claim 10 depends from claim 9, which depends from claims 8, 7, 6, 4, 2, and 1. That chain recites a first via coupled to the first line segment and a second via coupled to the second line segment (claim 2), and recites the third line segment (claim 4) and the sixth line segment (claim 8). It does not recite a third via. The claim therefore jumps from a “second via” to a “fourth via” with no third via in the sequence, making it unclear what structures are being counted.
Separately, claim 5 (also depending from claim 4) recites “a third via, arranged to electrically couple to the third line segment.” Claim 10 recites a differently numbered via also arranged to electrically couple to that same third line segment. The claim set does not establish whether the “third via” of claim 5 and the “fourth via” of claim 10 are the same via, two distinct vias on the same segment, or alternatives. A person of ordinary skill in the art cannot determine the metes and bounds of claim 10.
Applicant may overcome this rejection by:
reciting the vias with consistent ordinal numbering that matches the structures actually present in the claim 10 chain, and
specifying the relationship, if any, between the via coupled to the third line segment in claim 10 and the third via of claim 5 (or by placing claim 10 in a chain that includes claim 5 if a third via is intended).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim Rejections - 35 USC § 103
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Won (US 20180107539), in view of Chi et al. (US 20220277785; “Chi”).
Regarding independent claim 1, Won discloses a memory device, comprising:
a first bit line set, comprising a first bit line and a second bit line (para. 31; “8 bit line pairs BL and BLB (not shown) may be selected based on a one-time column selection signal CYi”);
a first column selection circuit, coupled to the first bit line and the second bit line (Fig. 3; See also para 36; “transfer the sensed and amplified data to the segment data line pair SIO and SIOB through switches (e.g., transistors M1 and M2) that are turned on when the corresponding column selection signal CYi is enabled.”);
a first data line, comprising a first line segment coupled to the first column selection circuit (para. 31; “ 8 data may be transferred from the 8 bit line pairs BL and BLB to the local data lines LIOi<0:7> through the segment data lines SIO<0:7>.”);
wherein the first column selection circuit is configured to electrically connect the first bit line to the first line segment for transmitting a first bit of normal data to the first line segment (para. 35; “when one (e.g., a first column selection signal CYi<0>) among a plurality of column selection signals CYi is selected, 8 data may be transferred from the memory cells that are disposed in a cell matrix (e.g., a second cell matrix MAT1) corresponding to the enabled word lien WL to a bit line pair BL and BLB. The 8 data that are transferred to the bit line pair BL and BLB may be sensed and amplified in a bit line sense amplifier BLSA and transferred to the segment data line pair SIO<0:7> and SIOB<0:7>, respectively.”),
Won discloses a second segment data line that carries parity bits from bit lines to an ECC device, but is silent with respect to that segment being coupled to the same first column selection circuit and that the first column selection circuit electrically connects the second bit line for the ECC transmission.
However, Chi teaches and a second data line, comprising a second line segment coupled to the first column selection circuit (Fig. 11; See also para. 28; “The first end of each switch tube T1 is used as a bit line connection port, a second terminal of each switch tube T1 is used as an input and output port, and control terminals of the 4 switch tubes T1 are interconnected to form one control port”.);
and to electrically connect the second bit line to the second line segment for transmitting a first bit of Error Correction/Detection data to the second line segment (para. 71; “two adjacent bit lines are connected to different sense amplifier groups, and when read errors occur simultaneously on the two adjacent bit lines, error data may be detected and corrected by an ECC.”).
Won and Chi are from the same field of endeavor as applicant’s invention directed to semiconductor memory in which column selection moves array bits onto data lines and ECC/parity is used to catch errors on those bits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Won’s on-die ECC with a conventional column-select event, using Chi’s even/odd split so that one bit line of the set is connected to Won’s normal-data line segment and the other bit line of the same set is connected to Won’s parity line segment. Doing so yields both bits in one column cycle and puts adjacent errors on the two paths Chi already uses for ECC.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Won (US 20180107539), in view of Chi et al. (US 20220277785; “Chi”), and further in view of Whately et al. (US 20210042189; “Whately”).
Regarding claim 2, Won and Chi combined disclose the limitations of claim 1.
As applied, Won further discloses further comprising: a first via, arranged to electrically couple to the first line segment (para. 30; “a plurality of segment data lines SIO<0:7> may be disposed to intersect with the local data lines LIOi<0:7>. The local data lines LIOi<0:7> may be coupled to a DQ pad through an input/output sense amplifier IOSA.” It is well understood in the art that tapping a metal data-line segment to the next metal, pad, or bump with a via or contact is nothing more than ordinary DRAM I/O interconnect.);
a second via, arranged to electrically couple to the second line segment (para 32; “in the parity storing region 14, 8 bit line pairs BL and BLB (not shown) may be selected based on a one-time column selection signal CYi, and 8 parity bits may be transferred to the local data lines LIOE<0:7> through the segment data lines SIO<0:7>. The 8 parity bits transferred to the local data lines LIOE<0:7> may be, eventually, transferred to the ECC device” As above, it is well understood in the art that tapping a metal data-line segment to the next metal, pad, or bump with a via or contact is nothing more than ordinary DRAM I/O interconnect.);
Won discloses an IOSA/DQ path for normal data and an ECC device on ECCP but is silent as to a memory controller coupled to those to paths.
However, Whately teaches a memory controller, arranged to electrically couple to the first via and the second via for receiving the first bit of normal data and the first bit of ECC data during a normal data reading operation and a ECC data reading operation respectively (Fig. 1A; See also para; 25; “A host device can then retrieve the data and ECC values (request a read operation), the memory controller can read the data and ECC values from the memory device.”).
Won and Chi combined, remain same-field art (array/CSC/ECC). Whately is combined as pertinent to the controller receiving normal data and ECC on two paths. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to put a controller on those the two paths of the Won/Chi device so the controller can run the ECC check. Doing so is merely a routine engineering arrangement yielding predictable results.
Regarding claim 3, notwithstanding the rejection for indefiniteness above, Won, Chi and Whately combined disclose the limitations of claim 2.
As applied, Whately further discloses wherein the memory controller performs the ECC data reading operation after the normal data reading operation (Fig. 13A. See also para. 114; “After the read latency, a burst of read data can be received on data lines 1350-3. ECC data for the read data can be received immediately after the read data burst 1350-4.”).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Won (US 20180107539), in view of Chi et al. (US 20220277785; “Chi”), and further in view of Whately et al. (US 20210042189; “Whately”), and further in view of Yan et al. (US 20120257433; “Yan”).
Regarding claim 4, Won, Chi and Whately combined disclose the limitations of claim 2.
As applied, Won further discloses wherein the… column selection circuit is configured to electrically connect the third bit line to the third line segment for transmitting a second bit of ECC data to the third line segment (para 68; “when more parity bits than the burst length of a segment data are outputted, the parity storing region 440 may include at least two cell matrix arrays 440UA and 440UB. For example, the cell matrices MAT of a first cell matrix array 440UA may share first local data lines LIOE1<0:7>, and the cell matrices MAT of a second cell matrix array 440UB may share second local data lines LIOE2<0:7>.”),
and to electrically connect the fourth bit line to the second line segment for transmitting a third bit of ECC data to the second line segment (para. 71; “8 data may be transferred from the memory cells that are positioned in a second cell matrix MAT1 and a fifth cell matrix MAT4 through the first local data lines LIOE1<0:7> and the second local data lines LIOE2<0:7> of FIG. 12 and may be eventually transferred to an ECC device through one line (i.e., ECCP2<0>) among the first dedicated lines ECCP1<0:7> and the second dedicated lines ECCP2<0:7>. Therefore, the ECC device may perform an ECC operation of detecting and correcting an error of a detective memory cell by using the 9 parity bits that are transferred through the first dedicated lines ECCP1<0:7> and the second dedicated line ECCP2<0>”.
Won, Chi and Whately combined disclose a first data line with a first line segment carrying normal data and a second data line with a second line segment carrying Error Correction/Detection data, both under column selection, with a controller on the two paths. The combination is silent with respect to an explicit second column selection circuit.
However, Yan teaches wherein the first data line further comprises a third line segment (Fig. 15. See also para. 102; “SELBA<31:0>; are shared by block 0 and block 1, SELBB<31:0> (not depicted) are shared by block 2 and block 3,… and SELB<31:0> are shared by block 14 and block 15”),
and the memory device further comprises:
a second bit line set, comprising a third bit line and a fourth bit line (para. 102; “FIG. 15 depicts 64 columns for each block, with each column including 32 selection circuits 500 for selecting 32 bit lines to be connected to the local data lines.”);
a second column selection circuit, coupled to the third bit line and the fourth bit line (para. 23; “Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry”);
Won already uses extra column-select events and extra local lines when more parity bits are needed. Yan shows how to add another local-data-line group and another select rank so more bit lines can reach more local lines. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Won, Chi and Whately by adding I/O and parity capacity by using the extra select + extra local-line group as taught by Yan and assign those extra bits as further ECC bits.
Regarding claim 5, Won, Chi, Whately and Yan combined disclose the limitations of claim 4.
As applied, Won further discloses further comprising: a third via, arranged to electrically couple to the third line segment (The antecedent third line segment is disclosed by Won in claim 4 above. As noted previously in the Office action, it is well understood in the art that tapping a metal data-line segment to the next metal, pad, or bump with a via or contact is nothing more than ordinary DRAM I/O interconnect);
And also as applied, Whately further discloses wherein the memory controller is further arranged to receive the second bit of ECC data through the third via and to receive the third bit of ECC data through the second via during the ECC data reading operation (para. 116; “The method 1450 can also include receiving corresponding ECC values on re-tasked I/Os (e.g., DBI/DM) in parallel with the burst of read data 1450-2.”. Also see para. 34; “In response to the read command, data values and corresponding ECC codes (118/120) can be transferred from memory device to MC 104.”, “ECC values 120 can be transmitted with the data values 118.”).
Claims 6-10 are not rejected under 35 U.S.C. § 103 on the prior art combination applied above. These claims stand rejected on the ground of nonstatutory double patenting. Moreover, claim 10 is also rejected under 35 U.S.C. § 112(b), both as set forth above.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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