Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed July 16th, 2026 has been entered. Claims 1-6 and 8-21 are pending in this application. Applicant amended independent claims 1, 12, and 13 have been amended to further teach comparing a forward error-checking code to a reverse error-checking code to determine that a transmission error has occurred and, in response to determining that a transmission error has occurred, setting a flag in a memory.
Applicant’s amendments to the claims have been fully considered. However, upon further consideration of the amended claims, the 35 USC § 103 rejection previously set forth in the Office Action mailed May 13th, 2026, has been modified to further rely upon Whetsel (US 5,483,518).
Response to Arguments
Applicant's arguments filed July 16th, 2026 have been fully considered but they are not persuasive.
Applicant argues that Kessler in view of Entelis fails to teach or suggest comparing a forward error-checking code to a reverse error-checking code to determined that a transmission error has occurred and setting, in response to determining that a transmission error has occurred, a flag in a memory. Applicant further argues that Entelis, at most, teaches taking corrective action such as rereading data or requesting retransmission when check values do not match.
The rejection has been modified to further rely upon Whetsel for the limitations added by Applicant. Whetsell teaches receiving a CRC value and comparing the received CRC value with a CRC value calculated from received information. Whetsel also teaches that when the received and calculated CRC values do not match, an error has occurred in the information transferred from the transmitting device to the receiving device. In response to the CRC error, Whetsel sets a CRC error bit in a status register. Whetsel further explains that the CRC error bit indicated that the received CRC did not match the calculated CRC.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5, 8-13, 17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kessler et al. (US 10,884,972), hereinafter Kessler, in view of Entelis et al. (US 11,546,448), hereinafter Entelis, and further in view of Whetsel (US 5,483,518).
Regarding claim 1, Kessler teaches a device comprising:
an integrated circuit (Kessler, Abstract, line 4, “a node transceiver may include SPI circuitry”); and
a serial peripheral interface (SPI) communicatively coupled to the integrated circuit (Kessler, Abstract, lines 1-2, “systems and techniques for serial peripheral interface (SPI) functionality”; Fig. 2, SPI Transceiver 136), wherein the SPI comprises a Master In Slave Out (MISO) channel, and a Master Out Slave In (MOSI) channel (Kessler, Fig. 2 teaches a BCLK, MISO, MOSI, and SS; col. 11, lines 14-18, “As known in the art, the SPI protocol uses slave select (SS), clock (BCLK), master-out-slave-in (MOSI), and master-in-slave-out (MISO) data lines to provide data transfer, and pins corresponding to these four lines are illustrated in FIG. 2”),
wherein the MOSI channel is configured to:
receive payload data to be written (Kessler, Fig. 21, step 202; col. 34, lines 17-18, “the SPI host 150 may send write data to the local node 142 via the MOSI line of the local SPI connection”); and
wherein the integrated circuit is configured to:
provide, to the MISO channel, the reverse error-checking code (Kessler, col. 34, lines 19-20, “the local node 142 is sending the previously received read data to the SPI host 150 via the MISO line”).
Kessler fails to teach receive a forward error-checking code usable to identify data corruption within the payload data and wherein the integrated circuit is configured to: calculate a reverse error-checking code based on the payload data, wherein the reverse error-checking code is usable to identify data corruption within the payload data, compare the forward error-checking code to the reverse error-checking code to determine that a transmission error has occurred; and set, in response to determining that the transmission error has occurred, a flag in a memory.
However, Entelis, in an analogous art, teaches receive a forward error-checking code usable to identify data corruption within the payload data (Entelis, Abstract, lines 12-16, “The compressed frames may use the same or different protocol than the uncompressed ones, and may further carry an additional code such as metadata, error detection or correction code, or authentication related code”; col. 18, lines 58-62, “Each node is able to send and receive messages, but not simultaneously. A message or Frame consists primarily of the ID [identifier], which represents the priority of the message, and up to eight data bytes. A CRC, acknowledge slot [ACK] and other overhead are also part of the message”), and wherein the integrated circuit is configured to: calculate a reverse error-checking code based on the payload data, wherein the reverse error-checking code is usable to identify data corruption within the payload data (Entelis, col. 51, lines 48-56, “Error correction may generally be realized in two different ways: Automatic Repeat Request (ARQ) [sometimes also referred to as backward error correction] -- This is an error control technique whereby an error detection scheme is combined with requests for retransmission of erroneous data. Every block of data received is checked using the error detection code used, and if the check fails, retransmission of the data is requested-this may be done repeatedly, until the data can be verified”).
Kessler and Entelis are both considered to be analogous to the claimed invention because both are in the same field of digital data communication that utilizes error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kessler to incorporate the teachings of Entelis by including the functionality of generating both forward and reverse error checking codes for the received payload data, where both codes are used to identify data corruption.
The suggestion/motivation for doing so would be to allow for error correction with and/or without retransmission (Entelis, col. 51, lines 61-65, “ARQ and FEC may be combined, such that minor errors are corrected without retransmission, and major errors are corrected via a request for retransmission: this is called hybrid automatic repeat-request [HARQ]”).
The combination of Kessler in view of Entelis, taken singly or combined, fails to teach or suggest compare the forward error-checking code to the reverse error-checking code to determine that a transmission error has occurred; and set, in response to determining that the transmission error has occurred, a flag in a memory.
However, Whetsel, in an analogous art, teaches compare the forward error-checking code to the reverse error-checking code (Whetsel, col. 31, lines 59-62, “the RCASP calculates its own CRC on the address and command fields received in the header and compares the calculated CRC against the CRC received in the select protocol”) to determine that a transmission error has occurred (Whetsel, col. 31, lines 64-67, “If a mismatch occurs between the received CRC and the calculated CRC, an error has occurred in the address and/or command fields transferred from the PSBM to the RCASP”); and set, in response to determining that the transmission error has occurred, a flag in a memory (Whetsel, col. 32, lines 1-2, “In response to a CRC mismatch error the RCASP sets a CRC error bit in the status register”).
Kessler, Entelis, and Whetsel are considered to be analogous to the claimed invention because they are in the same field of electronic communication systems using error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kessler in view of Entelis to incorporate the teachings of Whetsel by including the functionality of CRC comparison and indicating an error status via a flag or bit.
The suggestion/motivation for doing so would be to indicate an error in transmitted data when a received CRC does not match a calculated CRC.
Regarding claim 2, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, wherein the forward error-checking code or the reverse error-checking code comprises a cyclic redundancy check (Kessler, col. 15, lines 10-11, “In some embodiments, the synchronization control frame 180 may include a cyclic redundancy check (CRC) field”).
Regarding claim 5, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, wherein the integrated circuit is further configured to calculate the reverse error-checking code while the payload data is being received by the MOSI channel. Neither Kessler nor Entelis or Whetsel teach the claim, however Kessler teaches SPI serial communication and Entelis teaches CRC generated from payload data. CRC generation in serial communication systems would be conventional behavior.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kessler to incorporate the teachings of Entelis, further in view of Whetsel, by including the functionality of performing CRC or error-checking code calculations while payload data is received by the MOSI channel.
The suggestion/motivation for doing so would be to reduce latency and provide more efficient communication.
Regarding claim 8, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, wherein the SPI is a four-wire interface, and wherein the SPI further comprises a Slave Select (SSN) channel interface (Kessler, col. 11, lines 14-18, “As known in the art, the SPI protocol uses slave select (SS), clock (BCLK), master-out-slave-in (MOSI), and master-in-slave-out (MISO) data lines to provide data transfer, and pins corresponding to these four lines are illustrated in FIG. 2”).
Regarding claim 9, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, wherein the MOSI channel is further configured to receive a read address within the integrated circuit to be read from (Kessler, Abstract, lines 5-10, “SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver”; SPI commands could include read address information for accessing data), and wherein the integrated circuit is further configured to: calculate a secondary reverse error-checking code based on the read address and secondary payload data (Entelis, Abstract, lines 12-16, “The compressed frames may use the same or different protocol than the uncompressed ones, and may further carry an additional code such as metadata, error detection or correction code, or authentication related code”), wherein the secondary payload data is stored within the integrated circuit at the read address (Kessler, Abstract, lines 5-10, “SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver”; SPI commands could include read address information for accessing data, as well as the data stored at the read address), and wherein the secondary reverse error checking code is usable to identify data corruption within the read address or the secondary payload data (Entelis, col. 51, lines 48-56, “Error correction may generally be realized in two different ways: Automatic Repeat Request (ARQ) [sometimes also referred to as backward error correction] -- This is an error control technique whereby an error detection scheme is combined with requests for retransmission of erroneous data. Every block of data received is checked using the error detection code used, and if the check fails, retransmission of the data is requested-this may be done repeatedly, until the data can be verified”); and provide, to the MISO channel, the secondary payload data read and the secondary reverse error-checking code (Kessler, col. 34, lines 19-20, “the local node 142 is sending the previously received read data to the SPI host 150 via the MISO line”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kessler to incorporate the teachings of Entelis by including the functionality of generating reverse error checking codes for the received payload data, where both codes are used to identify data corruption.
The suggestion/motivation for doing so would be to allow for error correction with and/or without retransmission (Entelis, col. 51, lines 61-65, “ARQ and FEC may be combined, such that minor errors are corrected without retransmission, and major errors are corrected via a request for retransmission: this is called hybrid automatic repeat-request [HARQ]”).
Regarding claim 10, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, wherein the MOSI channel is further configured to receive an indication of whether a read routine or a write routine is to be performed by the integrated circuit (Kessler, Abstract, lines 5-10, “SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver”). It would have been obvious that the commands received via the SPI circuitry includes indications that specify whether read or write operations are to be performed, since read/write commands are conventional in SPI communication systems.
Regarding claim 11, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 10, wherein the reverse error-checking code does not match the forward error-checking code when a bit-flip has occurred in the indication of whether a read routine or a write routine is to be performed by the integrated circuit (Entelis, col. 50, lines 17-20, “On retrieval, the calculation is repeated and, in the event the check values do not match, corrective action can be taken against data corruption. CRCs can be used for error correction”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kessler to incorporate the teachings of Entelis by including the functionality of a bit flip in a read/write indication would result in mismatch between transmitted and calculated error-checking codes.
The suggestion/motivation for doing so would be because CRC error detection techniques are designed to detect corruption in transmitted data.
Claim 12 is a method with limitations similar to the device of claim 1, and is rejected under the same rationale.
Regarding claim 13, Kessler teaches a system comprising:
a controller; and
a subcontroller comprising an integrated circuit (Kessler, col. 26, lines 13-19, “node 102 may communicate with an SPI device via the SPI transceiver 136 included in the node transceiver 120. In some embodiments, the SPI device may be coupled to the SPI transceiver 136 via the pins of the node transceiver 120. In such embodiments, the SPI device may act as the SPI host while the node 102 acts as the SPI slave”; the SPI device or host equates to a controller and the SPI slave or node transceiver equates to a subcontroller comprising an integrated circuit),
wherein the subcontroller and the controller are communicatively coupled over a serial peripheral interface (SPI) communicatively coupled to the integrated circuit (Kessler, Abstract, lines 1-2, “systems and techniques for serial peripheral interface (SPI) functionality”; Fig. 2, SPI Transceiver 136), wherein the SPI comprises a Master In Slave Out (MISO) channel, and a Master Out Slave In (MOSI) channel (Kessler, Fig. 2 teaches a BCLK, MISO, MOSI, and SS; col. 11, lines 14-18, “As known in the art, the SPI protocol uses slave select (SS), clock (BCLK), master-out-slave-in (MOSI), and master-in-slave-out (MISO) data lines to provide data transfer, and pins corresponding to these four lines are illustrated in FIG. 2”),
wherein the MOSI channel is configured to:
receive payload data to be written (Kessler, Fig. 21, step 202; col. 34, lines 17-18, “the SPI host 150 may send write data to the local node 142 via the MOSI line of the local SPI connection”); and
wherein the integrated circuit is configured to:
provide, to the MISO channel, the reverse error-checking code (Kessler, col. 34, lines 19-20, “the local node 142 is sending the previously received read data to the SPI host 150 via the MISO line”).
Kessler fails to teach receive a forward error-checking code usable to identify data corruption within the payload data and wherein the integrated circuit is configured to: calculate a reverse error-checking code based on the payload data, wherein the reverse error-checking code is usable to identify data corruption within the payload data, compare the forward error-checking code to the reverse error-checking code to determine that a transmission error has occurred; and set, in response to determining that the transmission error has occurred, a flag in a memory.
However, Entelis, in an analogous art, teaches receive a forward error-checking code usable to identify data corruption within the payload data (Entelis, Abstract, lines 12-16, “The compressed frames may use the same or different protocol than the uncompressed ones, and may further carry an additional code such as metadata, error detection or correction code, or authentication related code”; col. 18, lines 58-62, “Each node is able to send and receive messages, but not simultaneously. A message or Frame consists primarily of the ID [identifier], which represents the priority of the message, and up to eight data bytes. A CRC, acknowledge slot [ACK] and other overhead are also part of the message”), and wherein the integrated circuit is configured to: calculate a reverse error-checking code based on the payload data, wherein the reverse error-checking code is usable to identify data corruption within the payload data (Entelis, col. 51, lines 48-56, “Error correction may generally be realized in two different ways: Automatic Repeat Request (ARQ) [sometimes also referred to as backward error correction] -- This is an error control technique whereby an error detection scheme is combined with requests for retransmission of erroneous data. Every block of data received is checked using the error detection code used, and if the check fails, retransmission of the data is requested-this may be done repeatedly, until the data can be verified”).
Kessler and Entelis are both considered to be analogous to the claimed invention because both are in the same field of digital data communication that utilizes error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kessler to incorporate the teachings of Entelis by including the functionality of generating both forward and reverse error checking codes for the received payload data, where both codes are used to identify data corruption.
The suggestion/motivation for doing so would be to allow for error correction with and/or without retransmission (Entelis, col. 51, lines 61-65, “ARQ and FEC may be combined, such that minor errors are corrected without retransmission, and major errors are corrected via a request for retransmission: this is called hybrid automatic repeat-request [HARQ]”).
The combination of Kessler in view of Entelis, taken singly or combined, fails to teach or suggest compare the forward error-checking code to the reverse error-checking code to determine that a transmission error has occurred; and set, in response to determining that the transmission error has occurred, a flag in a memory.
However, Whetsel, in an analogous art, teaches compare the forward error-checking code to the reverse error-checking code (Whetsel, col. 31, lines 59-62, “the RCASP calculates its own CRC on the address and command fields received in the header and compares the calculated CRC against the CRC received in the select protocol”) to determine that a transmission error has occurred (Whetsel, col. 31, lines 64-67, “If a mismatch occurs between the received CRC and the calculated CRC, an error has occurred in the address and/or command fields transferred from the PSBM to the RCASP”); and set, in response to determining that the transmission error has occurred, a flag in a memory (Whetsel, col. 32, lines 1-2, “In response to a CRC mismatch error the RCASP sets a CRC error bit in the status register”).
Kessler, Entelis, and Whetsel are considered to be analogous to the claimed invention because they are in the same field of electronic communication systems using error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kessler in view of Entelis to incorporate the teachings of Whetsel by including the functionality of CRC comparison and indicating an error status via a flag or bit.
The suggestion/motivation for doing so would be to indicate an error in transmitted data when a received CRC does not match a calculated CRC.
Claim 17 is a system with limitations similar to the device of claim 5, and is rejected under the same rationale.
Claim 20 is a system with limitations similar to the device of claim 8, and is rejected under the same rationale.
Regarding claim 21, the combination of Kessler in view of Entelis, further in view of Whetsel teaches the device of claim 1, wherein the SPI further comprises a clock (SCLK) channel (Kessler, Fig. 2 teaches a BCLK, which equates to a BCLK channel), wherein the SCLK channel is configured to receive a clock signal, wherein the MOSI channel is configured to receive the payload data to be written during a plurality of first clock cycles of the clock signal (Kessler, Fig. 21, step 202; col. 34, lines 17-18, “the SPI host 150 may send write data to the local node 142 via the MOSI line of the local SPI connection”), wherein the integrated circuit is configured to provide the reverse error-checking code to the MISO channel during a plurality of second clock cycles of the clock signal, and wherein the second clock cycles occur after the first clock cycles (Kessler, col. 34, lines 19-20, “the local node 142 is sending the previously received read data to the SPI host 150 via the MISO line”).
Claims 3-4 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kessler in view of Entelis, further in view of Whetsel, as applied to claims 1 and 13 above, and further in view of Zhixian Lin (CN114966618) (English translation relied upon), hereinafter Lin.
Regarding claim 3, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, but fails to teach wherein the device is a laser driver within a lidar device that comprises a plurality of light emitters, wherein the payload data comprises data usable to control emissions by the plurality of light emitters, and wherein the payload data comprises a firing selection of a subset of the plurality of light emitters, a charging voltage or charging current for capacitors used to fire one or more of the plurality of light emitters, a firing time for one or more of the plurality of the light emitters, or a firing power used to fire one or more of the plurality of light emitters.
However, Lin, in an analogous art, teaches wherein the device is a laser driver within a lidar device (Lin, Abstract, lines 1-2, “The invention relates to the field of automobile laser radars, in particular to an DANIELLIN type automobile laser radar system”) that comprises a plurality of light emitters, wherein the payload data comprises data usable to control emissions by the plurality of light emitters (Lin, claim 2, line 4, “laser emission module (103): initializing parameters and emitting laser by using a laser emitter VCSEL”), and wherein the payload data comprises a firing selection of a subset of the plurality of light emitters (Lin, claim 8, lines 1-2, “The DANIELLIN-type automotive lidar system using a MIPI and HSSL communication interface of claim 7, wherein: the laser radar is DANIELLIN; the laser radar ranging mode is pulse ranging”), a charging voltage or charging current for capacitors used to fire one or more of the plurality of light emitters, a firing time for one or more of the plurality of the light emitters (Lin, claim 7, lines 1-2, “The DANIELLIN-type automotive lidar system using a MIPI and HSSL communication interface of claim 6, wherein: in the flight time measuring method, a laser pulse sent by a laser radar starts to time”), or a firing power used to fire one or more of the plurality of light emitters.
Kessler, Entelis, Whetsel, and Lin are considered to be analogous to the claimed invention because they are in the same field of communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kessler in view of Entelis, further in view of Whetsel, to incorporate the teachings of Lin by including the functionality of a laser driver in a lidar device comprising data used to control the emission of light emitters, and various parameters pertaining to the light emitters.
The suggestion/motivation for doing so would be to improve the reliability of lidar device communication.
Regarding claim 4, the combination of Kessler in view of Entelis, further in view of Whetsel, further in view of Lin teaches the device of claim 3, wherein the lidar device is used for object detection and avoidance within an autonomous vehicle (Lin teaches an automative lidar system used for driving sensors in automobiles).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kessler in view of Entelis, further in view of Whetsel, to incorporate the teachings of Lin by including the functionality of the lidar device being used of vehicle object detection and avoidance.
The suggestion/motivation for doing so would be to improve the reliability of lidar device communication in vehicle sensors.
Claim 15 is a system with limitations similar to the device of claim 3, and is rejected under the same rationale.
Claim 16 is a system with limitations similar to the device of claim 4, and is rejected under the same rationale.
Claims 6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kessler in view of Entelis, further in view of Whetsel, as applied to claims 1 and 13 above, and further in view of Wang et al. (CN121029669) (English translation relied upon), hereinafter Wang.
Regarding claim 6, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the device of claim 1, but fails to teach wherein the forward error-checking code or the reverse error-checking code comprises a cyclic redundancy check based on a 9-bit polynomial.
However, Wang, in an analogous art, teaches wherein the forward error-checking code or the reverse error-checking code comprises a cyclic redundancy check based on a 9-bit polynomial (Wang, page 5, line 28, “In step 105251, the CRC algorithm uses CRC-8/MAXIM, the polynomial is 0x31 (x8+x5+x4+1)”).
Kessler, Entelis, Whetsel, and Wang are considered to be analogous to the claimed invention because they are in the same field of communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kessler in view of Entelis, further in view of Whetsel, to incorporate the teachings of Wang by including the functionality of a CRC check based on a 9-bit polynomial.
The suggestion/motivation for doing so would be that selecting a CRC polynomial is a design choice that affects error detection capability and the reliability of the communication system.
Claim 18 is a system with limitations similar to the device of claim 6, and is rejected under the same rationale.
Claim 19 is a system with limitations similar to the device of claim 7, and is rejected under the same rationale.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kessler in view of Entelis, further in view of Whetsel, as applied to claim 13 above, and further in view of Cao Xun Yan Yachao (CN114760008) (English translation relied upon), hereinafter Yan Yachao.
Regarding claim 14, the combination of Kessler in view of Entelis, further in view of Whetsel, teaches the system of claim 13, but fails to teach wherein the payload data is received within a second byte and a third byte of a first data packet by the MOSI channel, wherein the forward error-checking code is received within a fourth byte of the first data packet by the MOSI channel, and wherein the reverse error-checking code is provided within a first byte of a second data packet to the MISO channel.
However, Yan Yachao, in an analogous art, teaches wherein the payload data is received within a second byte and a third byte of a first data packet by the MOSI channel, wherein the forward error-checking code is received within a fourth byte of the first data packet by the MOSI channel (Yan Yachao, claim 5, “A communication method for an SPI bus according to claim 1, characterized in that before said CRC operation on the target data of a packet, it further comprises: setting a set number of bytes in a memory for storing the space of the data packet; the first byte of the data packet stores a Header, and the other bytes except the first byte and the last byte store the target data; after the CRC operation is performed on the target data of the data packet to obtain a first check value, the method further includes: and placing the first check value behind the target data so that the last byte of the data packet stores the first check value”), and wherein the reverse error-checking code is provided within a first byte of a second data packet to the MISO (Yan Yachao, pages 4-5, Detailed Description, lines 5-15, “The invention provides a communication method for an SPI bus, which comprises the following steps as shown in figure 1: s101, performing CRC operation on target data of a data packet by an MCU to obtain a first check value; it should be noted that, in an application scenario of the present invention, the MCU is to write target DATA in a DATA packet, where the target DATA is DATA and has a length of N. Step S101 is a preparation work, and specifically, the MCU calculates the first check value CRC _ MCU of the target DATA. S102, starting SPI communication by the MCU, and sequentially sending each byte data in the target data to the FPGA; s103, the FPGA carries out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received previous byte data so as to update the second check value; specifically, after the MCU sends a first byte DATA (1), the FPGA receives the DATA (1) at the moment, and before the MCU sends the next byte, the FPGA performs CRC operation on the received DATA [1) to obtain a second check value CRC _ TEMP; and then the MCU repeats the steps and repeats N-1 times, so that the DATA with the length of N can be sent out, and the FPGA carries out CRC operation on the basis of the second check value CRC _ TEMP every time the FPGA receives one byte, so as to obtain a new second check value CRC _ TEMP”).
Kessler, Entelis, Whetsel, and Yan Yachao are considered to be analogous to the claimed invention because they are in the same field of transmitting data packets.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kessler in view of Entelis, further in view of Whetsel to incorporate the teachings of Yan Yachao by including the functionality of a structured data packet.
The suggestion/motivation for doing so would be for efficient SPI packet communication.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Koshiyama et al. (US 8,683,290) teaches error correction and detection, where upon detecting an error, corrected data can be saved, and a validity flag test is performed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRACE V BRADEN/
Patent Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
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