DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
(1) Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,191,655. Although the claims at issue are not identical, they are not patentably distinct from each other. All claim limitations of the current application are recited in the patented claims. The patented claims disclose an electrostatic discharge protection circuit, comprising: a plurality of transistors comprising a first transistor and a second transistor; a pad; an ESD clamp; a stack of transistors connected between the first/second transistor and ESD clamp; and a plurality of switches connected to the gates of the first/second transistor.
(2) Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,862968. Although the claims at issue are not identical, they are not patentably distinct from each other. All claim limitations of the current application are recited in the patented claims. The patented claims disclose an electrostatic discharge protection circuit, comprising: a plurality of transistors comprising a first transistor and a second transistor; a pad; an ESD clamp; a stack of transistors connected between the first/second transistor and ESD clamp; and a plurality of switches connected to the gates of the first/second transistor.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore,
(1) the at least one other transistor in the stack of transistors recited in claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
(2) a third transistors recited in claims 4-7 must be shown or the features(s) canceled from the claims. No new matter should be entered.
(3) a third transistor, and at least one switch coupled between at least one of the first transistor and the second transistor or the third transistor and the ESD clamp recited in claim 11 must be shown or the feature(s) canceled from the claims. No new matter should be entered.
(4) a third transistor recited in claim 19 must be shown or the feature(s) canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 lines 1-2, the words “the plurality of transistor” should read – the plurality of transistors –
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 discloses that the second transistor is one transistor of a stack of transistors interposed between the ESD clamp and the first transistor. The Examiner interprets Fig. 3 as the following which best describes claim 3. N1 and N2 are first and second transistors of a plurality of transistors, 201 is a stack of transistors, and 302 is an ESD clamp. It is unclear to the Examiner how the second transistor is one of a stack of transistors. The stack of transistors 201 and the plurality of transistors N1, N2 are two separate elements described the specification and the claims. The Examiner is interpreting claim 3 as a stack of transistors connected between the gate of n1 and the ESD clamp 302 as shown in Fig. 3. Please make necessary amendments to reflect the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8-10, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. Publication No. US 2011/0194218.
Regarding claim 1, Chen discloses an electrostatic discharge (ESD) protection circuit, comprising:
a plurality of transistors coupled to each other [Fig. 2, Qn2, Qn1];
a pad coupled to a first transistor of the plurality of transistors [Fig. 1, VDDH, PS1]; and an ESD clamp coupled to a second transistor of the plurality of transistors and a ground [Fig. 2, transistor Qn3, R1, Qn4 is coupled to Qn1 and VSS].
Regarding claim 2, Chen discloses that a first terminal of the second transistor is coupled to a gate of the first transistor [Fig. 2, top terminal of Qn1 is electrically coupled to the gate of Qn2], a second terminal of the second transistor is coupled to the ESD clamp [Fig. 2, gate of Qn1 is coupled to Qn3], and a third terminal of the second transistor is coupled to the ground [Fig. 2, bottom terminal of Qn1 is coupled to VSS].
Regarding claim 8, Chen discloses that the ESD clamp has a resistor-capacitor (RC) time constant that is less than an RC time constant of a non-ESD event and greater than an RC time constant of an ESD event [Fig. 2, RC circuit comprising R1 and Qn4].
Regarding claim 9, Chen discloses that the ESD clamp comprises: a fourth transistor [Fig. 2, Qn3] coupled to the second transistor [Fig. 2, Qn1] and the ground [Fig. 2, VSS]; a capacitor [Fig. 2, Qn4] coupled between a gate of the fourth transistor and the second transistor; and a resistor [Fig. 2, R1] coupled between the gate of the fourth transistor and the ground.
Regarding claim 10, Chen discloses that the second transistor and the ESD clamp are connected to a voltage supply during non-ESD operation and are disconnected during a pad-to-ground ESD event [Fig. 3, the RC triggered Qn3 will turn on only during ESD event, and not connected to VDDH during normal operation].
Regarding claim 18, Chen discloses a method for operating an electrostatic discharge (ESD) protection circuit, comprising:
receiving, at a pad [Fig. 2, VDDH] coupled to a first transistor [Fig. 2, Qn2] of a plurality of transistors [Fig. 2, Qn2, Qn1], an ESD voltage, enabling a second transistor [Fig. 2, Qn1] of the plurality of transistors and an ESD clamp [Fig. 2, R1, Qn4, Qn3], wherein the ESD clamp is coupled to the second transistor and a ground; and discharging a first current associated with the ESD voltage through the second transistor and ESD clamp [abstract, specification].
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the following reason: The prior art does not disclose a stack of transistors interposed between the ESD clamp and the first transistor. (Please Note: this allowed claim limitation is different than the current claim 3, claim 3 is allowable pending the amendments to claim 3 as indicated in 112 rejection above].
The following is an examiner’s statement of reasons for allowance of claims 4 and 20, pending the objection to the Drawings as shown above: The prior art does not comprise a third transistor of the plurality of transistors is coupled to the first transistor and the ground.
Claims 11-17 are allowed, pending the correction to Drawing Objection as shown above.
The following is an examiner’s statement of reasons for allowance of claim 11: The prior art does not disclose an electrostatic discharge (ESD) protection circuit, comprising: an ESD clamp coupled to a third transistor of the plurality of transistors and a ground; and at least one switch coupled between at least one of the first transistor and the second transistor or the third transistor and the ESD clamp. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838
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