DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed December 20, 2024.
Claims 1-26 are pending. Claims 1, 13 and 19 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on December 20, 2024 and November 14, 2025. These IDSs have been considered.
Drawings
The drawings are objected to because:
Figures 6-8 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Applicants Figures 6-8 are identical to U.S. 2020/0066345 Figures 6-8.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 11-15, 17, 19-21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by De Sandre (U.S. 2010/0054032).
Regarding independent claim 1, De Sandre discloses a system (Fig. 1) comprising:
an array of non-volatile memory cells arranged in rows and columns (Fig. 1: 2, see also page 2, par. 0027), wherein each non-volatile memory cell comprises a word line terminal (Fig. 1: WL) and a bit line terminal (Fig. 1: BL); and
a row circuit (Fig. 1: 5) to receive a row address (Fig. 1: DAS) and a bias voltage (Fig. 1: Vp) and to output the bias voltage when the row address corresponds to a row of the array associated with the row circuit (see page 2, par. 0028-0029), wherein the bias voltage is provided to terminals of non-volatile memory cells in the row of the array associated with the row circuit (Fig. 1: output of 5 is provided to word line terminals of the row of the array 2).
Regarding claim 2, De Sandre discloses wherein the terminals are word line terminals (Fig. 1: WL).
Regarding claim 3, De Sandre discloses wherein the terminals are control gate terminals (Fig. 1: each select transistor 3b of the array comprises control gate).
Regarding claim 4, De Sandre discloses wherein the row circuit received the row address during a read operation of one or more non-volatile memory cells in the row of the array associated with the row circuit (see Abstract).
Regarding claim 5, De Sandre discloses the limitations with respect to claim 1.
As discussed above, De Sandre’s system is substantially identical in structure to the claimed “system,” where the differences reside only in the remaining limitations relating to function of “the row circuit received the row address during a verify operation of one or more non-volatile memory cells in the row of the array associated with the row circuit.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). De Sandre’s system appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 6, De Sandre discloses wherein the bias voltage is generated by a word line bias generation circuit (Fig. 1: 6).
Regarding independent claim 13, De Sandre discloses a method comprising:
receiving, by a row decoder (Fig. 1: 5) coupled to an array of non-volatile memory cells arranged in rows and columns (Fig. 1: 2, see also page 2, par. 0027), a row address (Fig. 1: DAS) and a bias voltage (Fig. 1: Vp);
outputting, by the row decoder (Fig. 1: 5), the bias voltage when the row address corresponds to a row of the array associated with the row decoder (see page 2, par. 0028-0029); and
applying, by the row decoder the bias voltage to terminals of non-volatile memory cells in the row of the array associated with the row decoder (Fig. 1: output of 5 is provided to word line terminals of the row of the array 2).
Regarding claim 14, De Sandre discloses wherein the terminals are word line terminals (Fig. 1: WL).
Regarding claim 15, De Sandre discloses wherein the terminals are control gate terminals (Fig. 1: each select transistor 3b of the array comprises control gate).
Regarding claim 17, De Sandre discloses wherein the bias voltage is generated by a replica bias circuit (Fig. 1: 6).
Regarding independent claim 19, De Sandre discloses a method comprising:
applying a bias voltage to a terminal of a selected non-volatile memory cell (Fig. 1: output of 5 is provided to word line terminals of the row of the array 2);
activating a transistor comprising a first terminal coupled to a bit line terminal of the selected non-volatile memory cell and a second terminal (Fig. 1: transistor 3b comprising a first terminal coupled to BL trough 3a and a second terminal coupled to GND); and
generating a voltage at the second terminal of the transistor indicating a value stored in the selected non-volatile memory cell (see page 2, par. 0027).
Regarding claim 20, De Sandre discloses wherein the terminal of the selected non-volatile memory cell is a word line terminal (Fig. 1: WL).
Regarding claim 21, De Sandre discloses wherein the terminal of the selected non-volatile memory cell is a control gate terminal (Fig. 1: each select transistor 3b of the array comprises control gate).
Regarding claim 23, De Sandre discloses wherein the transistor and the selected non-volatile memory cell from a source-follower configuration (Fig. 1: 3).
Allowable Subject Matter
Claims 7-12, 16, 18, 22 and 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited word line bias generation circuit comprises: a load comprising a first terminal coupled to a voltage source and a second terminal; a select transistor comprising a first terminal coupled to the second terminal of the load, a gate, and a second terminal; a current source comprising a first terminal coupled to the second terminal of the select transistor and a second terminal coupled to ground; and an operational amplifier comprising a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to the second terminal of the select transistor, and an output coupled to the gate of the select transistor and to an output of the word line bias generation circuit, wherein the output of the word line bias generation circuit provides the bias voltage.
With respect to claim 9, there is no teaching or suggestion in the prior art of record to provide the recited word line bias generation circuit comprises: a load comprising a first terminal coupled to a voltage source and a second terminal; a reference memory cell comprising a bit line terminal coupled to the second terminal of the load, a word line terminal, and a source line terminal; a select transistor comprising a first terminal coupled to the source line terminal of the reference memory cell, a gate coupled to a control signal, and a second terminal coupled to ground; and an operational amplifier comprising a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to the source line terminal of the reference memory cell, and an output coupled to the word line terminal of the reference memory cell and to an output of the word line bias generation circuit, wherein the output of the word line bias generation circuit provides the bias voltage.
With respect to claim 11, there is no teaching or suggestion in the prior art of record to provide the recited word line bias generation circuit comprises: a load comprising a first terminal coupled to a voltage source and a second terminal; a select transistor comprising a first terminal coupled to the second terminal of the load, a gate, and a second terminal; a reference memory cell comprising a bit line terminal coupled to the second terminal of the select transistor and a source line terminal coupled to ground; and an operational amplifier comprising a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to the bit line terminal of the reference memory cell, and an output coupled to the gate of the select transistor and to an output of the word line bias generation circuit, wherein the output of the word line bias generation circuit provides the bias voltage.
With respect to claim 16, there is no teaching or suggestion in the prior art of record to provide the recited step of the bias voltage causes voltages of drains of floating gate transistors of the non-volatile memory cells in the row of the array associated with the row decoder to be approximately constant as temperature, process, or power supply changes.
With respect to claim 18, there is no teaching or suggestion in the prior art of record to provide the recited replica bias circuit comprises a reference memory cell originated from a same process as non-volatile memory cells in the array.
With respect to claim 22, there is no teaching or suggestion in the prior art of record to provide the recited bias voltage changes in response to a change in temperature to maintain an approximately constant drain-to-source voltage of the selected non-volatile memory cell.
With respect to claim 24, there is no teaching or suggestion in the prior art of record to provide the recited second terminal of the transistor is coupled to a load.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
Prosecution Insights