Prosecution Insights
Last updated: October 22, 2026
Application No. 18/991,653

MULTIPLE SINGULATED DIE TEST STRUCTURE AND METHODS OF FORMING AND USING THE SAME

Non-Final OA §102
Filed
Dec 22, 2024
Examiner
HOQUE, FARHANA AKHTER
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
769 granted / 894 resolved
+18.0% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
13 currently pending
Career history
907
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
51.3%
+11.3% vs TC avg
§102
37.8%
-2.2% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 894 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ranganathan et al. (U.S. Publication No. 2023/0296667 A1). With respect to claim 1, Ranganathan et al. discloses a die testing structure, comprising: a cold plate (see cold plate 130 shown in Fig. 1A), wherein the cold plate comprises: a plurality of sensors (para 0069, lines 1-10); a plurality of heaters (para 0039, lines 5-19), wherein each heater is located below a corresponding sensor (para 0069, lines 1-10); and a vacuum channel with a plurality of vacuum sub-channels located between each sensor (para 0047, lines 10-14); wherein the plurality of sensors, the plurality of heaters, and the plurality of vacuum sub-channels form a plurality of testing locations configured to receive a plurality of dies (para 0053, lines 1-11). With respect to claim 2, Ranganathan et al. discloses the die testing structure of claim 1, wherein the vacuum sub-channels are configured to secure the dies to the cold plate via suction forces (para 0047, lines 10-14). With respect to claim 3, Ranganathan et al. discloses the die testing structure of claim 1, further comprising a multiple singulated die holder configured to hold the plurality of dies in testing locations (para 0047, lines 10-14), wherein the multiple singulated die holder is configured to be positioned on the cold plate and includes vacuum sub-channels positioned to secure dies in each testing location via suction forces (para 0047, lines 10-14; ). With respect to claim 4, Ranganathan et al. discloses the die testing structure of claim 1, further comprising a plurality of die grooves to accommodate dies during testing (para 0053, lines 1-11). With respect to claim 5, Ranganathan et al. discloses the die testing structure of claim 4, wherein the plurality of die grooves are located within the cold plate (see cold plate 130 see Fig. 1A). With respect to claim 6, Ranganathan et al. discloses the die testing structure of claim 4, further comprising a multiple singulated die holder located between the cold plate and the dies (see cold plate 130 see Fig. 1A; para 0053, lines 1-11), wherein the plurality of die grooves are formed within the multiple singulated die holder (para 0039, lines 5-19). With respect to claim 7, Ranganathan et al. discloses the die testing structure of claim 4, further comprising a high thermal conductivity layer and a low thermal conductivity layer (see thermal active interposer 120 shown in Fig. 1A, coupled to the backside or top of device 110), wherein the plurality of die grooves are formed within the low thermal conductivity layer and the high thermal conductivity layer is located within each of the plurality of die grooves (claim 1, lines 8-14). With respect to claim 8, Ranganathan et al. discloses the die testing structure of claim 7, further comprising a substrate, wherein the low thermal conductivity layer is located above the substrate (para 0034, lines 1-11). With respect to claim 9, Ranganathan et al. discloses the die testing structure of claim 7, wherein the high thermal conductivity layer has a thermal conductivity of at least 80 W/m*K (see thermal active interposer 120 shown in Fig. 1A, coupled to the backside or top of device 110). With respect to claim 10, Ranganathan et al. discloses the die testing structure of claim 7, wherein the low thermal conductivity layer has a thermal conductivity of at most 0.05 W/m*K (see thermal active interposer 120 shown in Fig. 1A, coupled to the backside or top of device 110). With respect to claim 11, Ranganathan et al. discloses a die holder, comprising: a low thermal conductivity layer (para 0034, lines 1-11) and a plurality of grooves located within the low thermal conductivity layer (para 0040, lines 8-19), wherein each die groove includes a high thermal conductivity layer (para 0056, lines 4-19), and each die groove is configured to receive an die located above each high thermal conductivity layer (para 0034, lines 1-11). With respect to claim 12, Ranganathan et al. discloses the multiple singulated die holder of claim 11, further comprising a plurality of vacuum sub-channels (para 0047, lines 10-14), each vacuum sub-channel is configured to be connected to a vacuum source (para 0049, lines 1-11), wherein each die groove is connected to one of the plurality of vacuum sub-channels (para 0060, lines 1-8). With respect to claim 13, Ranganathan et al. discloses the multiple singulated die holder of claim 11, further comprising a cold plate (para 0060, lines 1-5), wherein the low thermal conductivity layer is located within the cold plate (see cold plate 130 see Fig. 1A). With respect to claim 14, Ranganathan et al. discloses the multiple singulated die holder of claim 11, further comprising a substrate located between a cold plate and the low thermal conductivity layer (see substrate 410 shown in Fig. 4 and cold plate 130 shown in Fig. 1A). With respect to claim 15, Ranganathan et al. discloses the multiple singulated die holder of claim 11, wherein the high thermal conductivity layer has a thermal conductivity of at least 80 W/m*K (para 0053, lines 1-11). With respect to claim 16, Ranganathan et al. discloses the multiple singulated die holder of claim 11, wherein the low thermal conductivity layer has a thermal conductivity of at most 0.05 W/m*K (para 0053, lines 1-11). With respect to claim 17, Ranganathan et al. discloses a method for forming a singulated die holder, comprising: forming a low thermal conductivity layer (para 0053, lines 1-11); patterning the low thermal conductivity layer to form a plurality of die grooves (see substrate 410 shown in Fig. 4 and cold plate 130 shown in Fig. 1A); forming a high thermal conductivity layer in each of the plurality of die grooves (para 0054, lines 1-11); and forming a plurality of vacuum sub-channels, wherein each vacuum sub-channel is connected to each die groove (see substrate 410 shown in Fig. 4 and cold plate 130 shown in Fig. 1A). With respect to claim 18, Ranganathan et al. discloses the method of claim 17, wherein forming the high thermal conductivity layer further comprises: thinning the high thermal conductivity layer to be co-planar with the low thermal conductivity layer (para 0035, lines 1-6). With respect to claim 19, Ranganathan et al. discloses the method of claim 17, further comprising applying a second low thermal conductivity layer above the low thermal conductivity layer and high thermal conductivity layer (para 0053, lines 1-11). With respect to claim 20, The method of claim 19, further comprising patterning the second low thermal conductivity layer such that the second low thermal conductivity layer is above the low thermal conductivity layer and the high thermal conductivity layer is located in the die grooves (see substrate 410 shown in Fig. 4 and cold plate 130 shown in Fig. 1A). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARHANA AKHTER HOQUE whose telephone number is (571)270-7543. The examiner can normally be reached Monday-Friday, 7:30am-4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman A Alkafawi can be reached at 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FARHANA A HOQUE/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Dec 22, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
97%
With Interview (+11.2%)
2y 4m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 894 resolved cases by this examiner. Grant probability derived from career allowance rate.

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