DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2024 has been considered by the examiner.
Drawings
The drawings were received on 12/22/24. These drawings are acceptable.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
‘access unit’ in claims 1, 12, and 16
‘activation unit’ in claims 1, 8, 12, and 16
‘ECC unit’ in claims 15 and 19.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The term “access unit” appears to be defined as ‘output size capability of the I/O circuitry’ based on paragraph [0050] of the present specification.
The term “activation unit” appears to be defined as ‘An amount of data of the memory cells coupled to the powered word line and read out by the row buffer for the bank’ based on paragraph [0049] of the present specification.
The term “ECC unit” appears to be defined as ‘may include hardware, software, or combination thereof to perform processes of identifying errors in data retrieved from the memory 102 and to potentially correct the errors’ based on paragraph [0035] of the present specification, and ‘The ECC unit 108 can be configured to utilize any type of error correction algorithm, process, or code, for example, Hamming codes, Hsiao codes, Reed-Solomon codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, low-density-parity-check codes, etc. The ECC unit 108 may utilize the ECCs to detect one or more errors of data bits for a read memory access of the memory 102 and further attempt to correct the one or more errors.’ based on paragraph [0038] of the present specification.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1- 14, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The examiner would like to point out that when substituting the definitions for the terms access unit (‘output size capability of the I/O circuitry’ based on paragraph [0050]) and activation unit (‘An amount of data of the memory cells coupled to the powered word line and read out by the row buffer for the bank’ based on paragraph [0049]) in the claims, the claims do not make sense to the examiner. This means that the interpreted language from the specification above are either incorrect or the claim language is inconsistent with the specification. The examiner requests clarification of these definitions and requests that applicant point out within the specification where these definitions can be found.
Claims 2-7 and 9-13 inherit the 35 U.S.C. 112 issues of independent claims 1 and 8 thus even without containing the questioned terminology, these claims are rejected for the same reasoning. Clarification of these issues is required for a proper search and comparison with the prior arts. As such these claims will not be considered with respect to the prior arts.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-14 and 15-20 of U.S. Patent No. 11,610,640. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims appear to be fully contained within the patented claims. Therefore a person having ordinary skill in the art at the time of filing of the present application would have been fully aware of the pending claims. See table below.
18991656
US 11610640
1. A method for error correction in a memory system, comprising: determining multiple error correction codes (ECCs) for an access data at a column address of a memory including a first ECC and at least one second ECC, wherein
the first ECC has data from an access unit subset of an activation unit of the memory, and wherein
the at least one second ECC has a data from the access unit and a data from the activation unit other than from the access unit.
8. A method for error correction in a memory system, comprising: determining multiple error correction codes (ECCs) for an access data at a column address of a memory including a first ECC and at least one second ECC, wherein
the first ECC has data from an access unit subset of an activation unit of the memory, and wherein
the at least one second ECC has a data from the access unit and a data from the activation unit other than from the access unit; and
attempting to correct an error in the access data using the at least one second ECC.
2. The method of claim 1, wherein determining the multiple ECCs for the access data comprises:
receiving the column address as an input to an ECC group function;
executing the ECC group function; and generating a result of the ECC group function configured to indicate the multiple ECCs associated with the column address from among a larger multiple of ECCs.
9. The method of claim 8, wherein determining the multiple error correction codes for the access data comprises:
receiving the column address as an input to an ECC group function;
executing the ECC group function; and generating a result of the ECC group function configured to indicate the multiple ECCs associated with the column address from among a larger multiple of ECCs.
3. The method of claim 2, wherein: executing the ECC group function comprises executing multiple hash functions using the column address, wherein each of the multiple hash functions is associated with a different one of the multiple ECCs; and generating the result of the ECC group function comprises generating a hash array for which a result of each of the multiple hash functions is associated with a position of multiple positions in the hash array and each of the multiple position is associated with one of the multiple ECCs.
10. The method of claim 9, wherein: executing the ECC group function comprises executing multiple hash functions using the column address, wherein each of the multiple hash functions is associated with a different one of the multiple ECCs; and generating the result of the ECC group function comprises generating a hash array for which a result of each of the multiple hash functions is associated with a position of multiple positions in the hash array and each of the multiple position is associated with one of the multiple ECCs.
4. The method of claim 1, wherein determining the multiple ECCs for the access data comprises determining column addresses for each bit of the at least one second ECC, and the method further comprises retrieving the at least one second ECC from the memory using the determined column addresses.
11. The method of claim 8, wherein determining the multiple ECCs for the access data comprises determining column addresses for each bit of the at least one second ECC, and the method further comprises retrieving the at least one second ECC from the memory using the determined column addresses.
5. The method of claim 1, wherein: the multiple ECCs include multiple second EECs including a third ECC and a fourth ECC, wherein the at least one second ECC is the third ECC, and attempting to correct the error in the access data using the at least one second ECC comprises attempting to correct the error in the access data using the third ECC, the method further comprising attempting to correct the error in the access data using the fourth ECC following failure to correct the error in the access data using the third ECC.
12. The method of claim 8, wherein: the multiple ECCs include multiple second EECs including a third ECC and a fourth ECC, wherein the at least one second ECC is the third ECC, and attempting to correct the error in the access data using the at least one second ECC comprises attempting to correct the error in the access data using the third ECC, the method further comprising attempting to correct the error in the access data using the fourth ECC following failure to correct the error in the access data using the third ECC.
6. The method of claim 1, further comprising: determining whether the error in the access data is repairable using the at least one second ECC, wherein attempting to correct the error in the access data using the at least one second ECC occurs in response to determining that the error in the access data is repairable using the at least one second ECC; and triggering a data reload for the access data in response to determining that the error in the access data is not repairable using the at least one second ECC.
13. The method of claim 8, further comprising: determining whether the error in the access data is repairable using the at least one second ECC, wherein attempting to correct the error in the access data using the at least one second ECC occurs in response to determining that the error in the access data is repairable using the at least one second ECC; and triggering a data reload for the access data in response to determining that the error in the access data is not repairable using the at least one second ECC.
7. The method of claim 6, further comprising determining whether the error is unrepairable for an nth ECC, wherein triggering the data reload for the access data occurs in response to determining that the error is unrepairable for an nth ECC.
14. The method of claim 13, further comprising determining whether the error is unrepairable for an nth ECC, wherein triggering the data reload for the access data occurs in response to determining that the error is unrepairable for an nth ECC.
15. A memory system, comprising:
an input/output (I/O) circuitry, wherein
the I/O circuitry
determines multiple error correction codes (ECCs) for an access data; and
an error correction code (ECC) unit coupled to the I/O circuitry, wherein
the ECC unit determines whether an error in the access data is repairable with at least one of the multiple ECCs.
15. A memory system, comprising:
an input/output (I/O) circuitry; and an error correction code (ECC) unit coupled to the I/O circuitry, wherein: the I/O circuitry is configured to implement operations comprising:
determining multiple error correction codes (ECCs) for an access data at a column address of a memory access; transmitting the access data to the EEC unit; and transmitting the multiple ECCs to the ECC unit; the ECC unit is configured to implement operations comprising:
determining whether an error in the access data is repairable with at least one of the multiple ECCs; and correcting the error in the access data in response to determining that the error in the access data is repairable with the at least one of the multiple ECCs.
16. The memory system of claim 15, wherein the I/O circuitry is configured to implement operations such that determining multiple ECCs comprises: determining a first ECC having data from an access unit subset of an activation unit of a memory subject to the memory access; and determining a second ECC having a data from the access unit and a data from the activation unit other than from the access unit.
16. The memory system of claim 15, wherein the I/O circuitry is configured to implement operations such that determining multiple ECCs comprises: determining a first ECC having data from an access unit subset of an activation unit of a memory subject to the memory access; and determining a second ECC having a data from the access unit and a data from the activation unit other than from the access unit.
17. The memory system of claim 15, wherein the I/O circuitry is configured to implement operations such that determining multiple ECCs comprises: receiving the column address as an input to an ECC group function; executing the ECC group function; and generating a result of the ECC group function configured to indicate the multiple ECCs associated with the column address from among a larger multiple of ECCs.
17. The memory system of claim 15, wherein the I/O circuitry is configured to implement operations such that determining multiple ECCs comprises: receiving the column address as an input to an ECC group function; executing the ECC group function; and generating a result of the ECC group function configured to indicate the multiple ECCs associated with the column address from among a larger multiple of ECCs.
18. The memory system of claim 17, wherein the I/O circuitry is configured to implement operations such that: executing the ECC group function comprises executing multiple hash functions using the column address, wherein each of the multiple hash functions is associated with a different one of the multiple ECCs; and generating the result of the ECC group function comprises generating a hash array for which a result of each of the multiple hash functions is associated with a position of multiple positions in the hash array and each of the multiple position is associated with one of the multiple ECCs.
18. The memory system of claim 17, wherein the I/O circuitry is configured to implement operations such that: executing the ECC group function comprises executing multiple hash functions using the column address, wherein each of the multiple hash functions is associated with a different one of the multiple ECCs; and generating the result of the ECC group function comprises generating a hash array for which a result of each of the multiple hash functions is associated with a position of multiple positions in the hash array and each of the multiple position is associated with one of the multiple ECCs.
19. The memory system of claim 15, wherein: the ECC unit is configured to implement operations such that determining whether the error in the access data is repairable with the at least one of the multiple ECCs comprises determining whether the error in the access data is repairable with a first ECC of the multiple ECCs; and the ECC unit is configured to implement operations further comprising selecting a second ECC of the multiple ECCs in response to determining that the error in the access data is not repairable with the first ECC, wherein determining whether the error in the access data is repairable with the at least one of the multiple ECCs further comprises determining whether the error in the access data is repairable with the second ECC, and wherein correcting the error in the access data comprises correcting the error in the access data using the second EEC in response to determining that the error in the access data is repairable with the second ECCs.
19. The memory system of claim 15, wherein: the ECC unit is configured to implement operations such that determining whether the error in the access data is repairable with the at least one of the multiple ECCs comprises determining whether the error in the access data is repairable with a first ECC of the multiple ECCs; and the ECC unit is configured to implement operations further comprising selecting a second ECC of the multiple ECCs in response to determining that the error in the access data is not repairable with the first ECC, wherein determining whether the error in the access data is repairable with the at least one of the multiple ECCs further comprises determining whether the error in the access data is repairable with the second ECC, and wherein correcting the error in the access data comprises correcting the error in the access data using the second EEC in response to determining that the error in the access data is repairable with the second ECCs.
20. The memory system of claim 15, wherein the I/O circuitry includes a bitline decoder, wherein the bitline decoder is configured to implement operations comprising determining the ECCs for the access data at the column address of the memory access.
20. The memory system of claim 15, wherein the I/O circuitry includes a bitline decoder, wherein the bitline decoder is configured to implement operations comprising determining the ECCs for the access data at the column address of the memory access.
Claims 8-14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,211,574. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims appear to be fully contained within the patented claims. Therefore a person having ordinary skill in the art at the time of filing of the present application would have been fully aware of the pending claims. See table below.
18991656
US 12211574
8. A method for error correction in a memory system, comprising: generating a representation of multiple error correction codes (ECCs) of an ECC group that are associated with an access data from a memory, wherein
the ECC group is associated with an activation unit of the memory having the access data.
1. A method for error correction in a memory system, comprising: generating a representation of multiple error correction codes (ECCs) of an ECC group that are associated with an access data from a memory, wherein the ECC group is associated with an activation unit of the memory having the access data; and
checking the access data for an error utilizing at least one of the multiple ECCs.
9. The method of claim 8, wherein generating the representation of the multiple ECCs of the ECC group that are associated with the access data from the memory comprises generating the representation of the multiple ECCs using a column address of a memory access corresponding to the access data.
2. The method of claim 1, wherein generating the representation of the multiple ECCs of the ECC group that are associated with the access data from the memory comprises generating the representation of the multiple ECCs using a column address of a memory access corresponding to the access data.
10. The method of claim 8, wherein generating the representation of the multiple ECCs of the ECC group that are associated with the access data from the memory comprises: executing an ECC group function; and generating a result of the ECC group function configured to indicate the multiple ECCs associated with the access data from among a larger multiple of ECCs.
3. The method of claim 1, wherein generating the representation of the multiple ECCs of the ECC group that are associated with the access data from the memory comprises: executing an ECC group function; and generating a result of the ECC group function configured to indicate the multiple ECCs associated with the access data from among a larger multiple of ECCs.
11. The method of claim 10, wherein: executing the ECC group function comprises executing multiple hash functions using a column address of a memory access corresponding to the access data, wherein each of the multiple hash functions is associated with a different one of the multiple ECCs; and generating the result of the ECC group function comprises generating a hash array for which a result of each of the multiple hash functions is associated with a position of multiple positions in the hash array and each of the multiple position is associated with one of the multiple ECCs.
4. The method of claim 3, wherein: executing the ECC group function comprises executing multiple hash functions using a column address of a memory access corresponding to the access data, wherein each of the multiple hash functions is associated with a different one of the multiple ECCs; and generating the result of the ECC group function comprises generating a hash array for which a result of each of the multiple hash functions is associated with a position of multiple positions in the hash array and each of the multiple position is associated with one of the multiple ECCs.
12. The method of claim 8, wherein the multiple ECCs includes: a first ECC having data from an access unit of the memory corresponding with using a column address of a memory access corresponding to the access data; and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.
5. The method of claim 1, wherein the multiple ECCs includes: a first ECC having data from an access unit of the memory corresponding with using a column address of a memory access corresponding to the access data; and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.
13. The method of claim 12, further comprising checking the access data for an error utilizing the at least one of the multiple ECCs comprises determining whether the access data has an error using the first ECC, the method further comprising: determining whether the error is correctable using the first ECC in response to determining that the access data has an error using the first ECC; determining whether the access data has an error using the second ECC in response to determining that the error is not correctable using the first ECC; and determining whether the error is correctable using the second ECC in response to determining that the access data has an error using the second ECC.
6. The method of claim 5, wherein checking the access data for an error utilizing the at least one of the multiple ECCs comprises determining whether the access data has an error using the first ECC, the method further comprising: determining whether the error is correctable using the first ECC in response to determining that the access data has an error using the first ECC; determining whether the access data has an error using the second ECC in response to determining that the error is not correctable using the first ECC; and determining whether the error is correctable using the second ECC in response to determining that the access data has an error using the second ECC.
14. The method of claim 13, wherein checking the access data for an error utilizing the at least one of the multiple ECCs comprises checking the access data for an error utilizing the second ECC, the method further comprising: correcting the error of the access data using the second ECC generating a final access data; and outputting the final access data to a component of a computing device from which a memory access request triggered the memory access.
7. The method of claim 5, wherein checking the access data for an error utilizing the at least one of the multiple ECCs comprises checking the access data for an error utilizing the second ECC, the method further comprising: correcting the error of the access data using the second ECC generating a final access data; and outputting the final access data to a component of a computing device from which a memory access request triggered the memory access.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 9619318 to Leininger et al. teaches a method for accessing a memory and a method for repairing a memory using error detection information for data element.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111
Prosecution Insights