DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 5, 10, and 14-15 are amended. Claims 1-17 are present for examination.
Response to Arguments
Applicant’s arguments, see pages 6-7, filed May 19, 2026, with respect to the rejection(s) of claim(s) 1 and 5-8 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kang (US 2018/0308850 A1).
Applicant’s arguments, see pages 7-9, filed May 19, 2026, with respect to the rejection(s) of claim(s) 2-4 and 9-17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kang (US 2018/0308850 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the slanted geometry of the isolation region 10i, further including gate structures 11/14 (e.g. wherein the semiconductor device comprises a plurality of isolation regions adjacent to a plurality of doped regions; wherein each isolation region has a smaller width at the bottom surface of the trench than at the top surface of the trench and further includes a gate structure). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0395455 A1) in view of Kang (US 2018/0308850 A1).
Claim 1, Kim discloses a semiconductor device (Fig. 3), comprising:
a substrate (substrate 101, para [0047], Fig. 3) having a trench (trench 105, para [0047], Fig. 3); and
a gate structure 200G in the trench 105 (buried gate structure 200G may be formed in the trench 105, para [0047], Fig. 3), wherein the gate structure 200G comprising:
a lower gate electrode 109 (gate structure 200G may include a lower buried portion LB consisting of first gate electrode 109, para [0049], Fig. 3);
an upper gate electrode 111 (second gate electrode 111, para [0056], Fig. 3) over the lower gate electrode 109 (upper buried portion UB is formed on the lower buried portion LB, para [0023], Fig. 3); and
a first dielectric layer (second barrier layer 110, para [0049], Fig. 3) partially disposed between the lower gate electrode 109 and the upper gate electrode 111 (110 is disposed between 109 and 111, Fig. 3); and
a first barrier layer (first barrier layer 108, para [0049]) partially disposed between the lower gate electrode 109 and the substrate 101 (108 is partially disposed between 109 and 101), wherein the first barrier layer 108 contacts the first dielectric layer 110 (first barrier layer 108 contacts the first dielectric layer 110).
Kim does not explicitly disclose a capping layer formed on the upper gate electrode, wherein the capping layer is in contact with the first dielectric layer and the upper gate electrode; and wherein a top surface of the capping layer is coplanar with a top surface of the first dielectric layer.
However, Kang (US 2018/0308850 A1) discloses a capping layer (Kang, capping layer 309, [0148], Fig. 9; Kim, Fig. 3) formed on the upper gate electrode (Kang, capping layer 309 is formed on the upper buried portion 308 which is an upper gate electrode, hereinafter, upper gate electrode 308, [0148], Fig. 9; Kim, Fig. 3), wherein the capping layer is in contact with the first dielectric layer and the upper gate electrode (Kang, capping layer 309 is in contact with the upper barrier 311T which is a first dielectric layer, hereinafter, first dielectric layer 311T and the upper gate electrode 308, [0148], Fig. 9; Kim, Fig. 3); and wherein a top surface of the capping layer is coplanar with a top surface of the first dielectric layer (Kang, a top surface of the capping layer 309 is coplanar with a top surface of the first dielectric layer 311T, [0148], Fig. 9; Kim, Fig. 3). The combination to utilize a capping layer in combination with the underlying gate electrode and dielectric layer allows for protection of the underlying buried gate electrode (Kang, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a capping layer in combination with the underlying gate electrode and dielectric layer to allow for protection of the underlying buried gate electrode (Kang, [0057]).
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Fig. 3 (Kim) – Illustrates a substrate 101 including a gate structure 200G in trench 105; wherein gate structure 200G comprises a lower gate electrode 109, an upper gate electrode 111 over the lower gate electrode 109, and a first dielectric layer 110 partially disposed between the lower gate electrode 109 and the upper gate electrode 111.
Claim 5, Kim/Kang discloses the semiconductor device (Kim, Fig. 3; Kang, Fig. 9) of claim 1.
Kim/Kang discloses a second dielectric layer (Kim, first barrier layer 108, para [0049]; Yedinak, Fig. 4A) partially disposed between the lower gate electrode 109 and the substrate 101 (Kim, 108 is partially disposed between 109 and 101; Yedinak, Fig. 4A);
wherein the first dielectric layer 110 is spaced apart from the substrate 101 by the second dielectric layer 108 (110 is spaced apart from 101 by 108); and the first dielectric layer 110 and the second dielectric layer 108 comprises different densities (Kim, first and second barrier layers 108/110 may be made of different materials which inherently will have different densities; first barrier layers 108 are tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN), para [0054] and second barrier layers 110 are tantalum nitride (TaN) or titanium nitride (TiN), para [0056]; Yedinak, Fig. 4A).
Kim does not explicitly disclose wherein the second dielectric layer is conformally formed on a bottom surface and a sidewall of the trench; wherein a top surface of the second dielectric layer, the top surface of the capping layer, and the top surface of the first dielectric layer are coplanar with each other.
However, Kang discloses wherein the second dielectric layer is conformally formed on a bottom surface and a sidewall of the trench (Kang, work function liner 310L is a second dielectric layer, hereinafter, second dielectric layer 310L and is conformally formed on a bottom surface and a sidewall of the trench 305, [0148], Fig. 9; Kim, Fig. 3);
wherein a top surface of the second dielectric layer, the top surface of the capping layer, and the top surface of the first dielectric layer are coplanar with each other (Kang, a top surface of the second dielectric layer 310L, the top surface of the capping layer 309, and the top surface of the first dielectric layer 311T is coplanar with each other, [0148], Fig. 9; Kim, Fig. 3). The combination to utilize another dielectric layer in combination with the capping layer, underlying gate electrode, and dielectric layer allows for protection of the underlying buried gate electrode (Kang, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize another dielectric layer in combination with the capping layer, underlying gate electrode, and dielectric layer to allow for protection of the underlying buried gate electrode (Kang, [0057]).
Claim 6, Kim/Kang discloses the semiconductor device (Kim, Fig. 3; Kang, Fig. 9) of claim 1.
Kim/Kang discloses wherein the first dielectric layer 110 directly contacts the lower gate electrode 109 and the upper gate electrode 111 (Kim, 110 is disposed between and directly contacts 109 and 111; Yedinak, Fig. 4A).
Claim 7, Kim/Kang discloses the semiconductor device (Kim, Fig. 3; Kang, Fig. 9) of claim 1.
Kim/Kang discloses wherein the gate structure 200G is disposed in an active region 104 of the substrate 101 (Kim, gate structure 200G is disposed in an active region 104 of the substrate 101, para [0048]; Kang, Fig. 9).
Claim 8, Kim/Kang discloses the semiconductor device (Kim, Fig. 3; Kang, Fig. 9) of claim 1.
Kim/Kang discloses wherein the gate structure 200G is disposed in an isolation region 102 of the substrate 101 (Kim, gate structure 200G is disposed in an isolation region 102 of the substrate 101, para [0048]; Kang, Fig. 9).
Claim 2, 10-11, 14, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang in view of Yedinak (US 2009/0008706 A1).
Claim 2, Kim/Kang discloses the semiconductor device (Kim, Fig. 3; Kang, Fig. 9) of claim 1.
Kim/Kang does not explicitly disclose wherein the lower gate electrode and the upper gate electrode are configured to receive different voltages.
However, Yedinak discloses a semiconductor device (Fig. 4A) with lower gate electrode G2 and upper gate electrode G1 that are configured to receive different voltages. G2 is biased independently of the upper gate terminal G1 and does not receive the same signal that drives the switching transistor (Yedinak, para [0118])
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to allow the upper and lower gate structures to be configured to receive different voltages in an attempt to improve switching speed and reduce gate-to-drain capacitance (Yedinak, para [0118]).
Claim 10, Kim discloses a semiconductor device (Fig. 3), comprising:
a substrate (substrate 101, para [0047], Fig. 3) having a trench (trench 105, para [0047], Fig. 3); and
a gate structure 200G in the trench 105 (buried gate structure 200G may be formed in the trench 105, para [0047], Fig. 3), wherein the gate structure 200G comprising:
a lower gate electrode 109 (gate structure 200G may include a lower buried portion LB consisting of first gate electrode 109, para [0049], Fig. 3);
an upper gate electrode 111 (second gate electrode 111, para [0056], Fig. 3) over the lower gate electrode 109 (upper buried portion UB is formed on the lower buried portion LB, para [0023], Fig. 3); and
a first barrier layer (first barrier layer 108, para [0049]) disposed between the lower gate electrode 109 and the substrate 101 (108 is partially disposed between 109 and 101), wherein the first barrier layer 108 contacts the first dielectric layer 110 (first barrier layer 108 contacts the first dielectric layer 110).
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Fig. 3 (Kim) – Illustrates a substrate 101 including a gate structure 200G in trench 105; wherein gate structure 200G comprises a lower gate electrode 109, an upper gate electrode 111 over the lower gate electrode 109, and a first dielectric layer 110 partially disposed between the lower gate electrode 109 and the upper gate electrode 111.
Kim does not explicitly disclose wherein the lower gate electrode and the upper gate electrode are configured to receive different voltages.
However, Yedinak discloses a semiconductor device (Fig. 4A) with lower gate electrode G2 and upper gate electrode G1 that are configured to receive different voltages. G2 is biased independently of the upper gate terminal G1 and does not receive the same signal that drives the switching transistor (Yedinak, para [0118]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to allow the upper and lower gate structures to be configured to receive different voltages in an attempt to improve switching speed and reduce gate-to-drain capacitance (Yedinak, para [0118]).
Kim/Yedinak does not disclose a first dielectric layer disposed between the lower gate electrode and the substrate; and
a second dielectric layer disposed in the first dielectric layer, wherein the second dielectric layer comprises a base portion formed between the lower gate electrode and the upper gate electrode, and an extending portion extending from the base portion and in contact with the first dielectric layer, such that the first dielectric layer is in contact with the first barrier layer and the extending portion of the second dielectric layer.
However, Kang discloses a first dielectric layer disposed between the lower gate electrode and the substrate (Kang, first dielectric layer 306 is disposed between the lower gate electrode 307 and the substrate 301, [0148], Fig. 9; Kim, Fig. 3; Yedinak, Fig. 4A); and
a second dielectric layer disposed in the first dielectric layer (Kang, second dielectric layer 311T is in the first dielectric layer 306, [0148], Fig. 9; Kim, Fig. 3; Yedinak, Fig. 4A), wherein the second dielectric layer comprises a base portion formed between the lower gate electrode and the upper gate electrode (Kang, second dielectric layer 311T comprises a base portion formed between the lower gate electrode 307 and the upper gate electrode 308, [0148], Fig. 9; Kim, Fig. 3; Yedinak, Fig. 4A), and an extending portion extending from the base portion and in contact with the first dielectric layer, such that the first dielectric layer is in contact with the first barrier layer and the extending portion of the second dielectric layer (Kang, second dielectric layer 311T comprises an extending portion extending from the base portion and in contact with the first dielectric layer 306, such that the first dielectric layer 306 is in contact with the first barrier layer 310L and the extending portion of the second dielectric layer 311T, [0148], Fig. 9; Kim, Fig. 3; Yedinak, Fig. 4A). The combination to utilize an additional dielectric layer in combination with the lower and upper buried gate electrodes allows for protection of the underlying buried gate electrode (Kang, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional dielectric layer in combination with the lower and upper buried gate electrodes to allow for protection of the underlying buried gate electrode (Kang, [0057]).
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Fig. 4A (Yedinak) – Illustrates a semiconductor device 400A with a dual gate structure within trench 402, further consisting of lower gate electrode G2 and upper gate electrode G1 that are configured to receive different voltages.
Claim 11, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 10.
Kim/Yedinak/Kang discloses wherein the lower gate electrode 109 and the upper gate electrode 111 are spaced apart from the substrate 101 by different distances (Kim, 109 is closer to 101 than 111, Fig. 3).
Claim 14, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 10.
Kim/Yedinak/Kang disclose a capping layer (Kang, capping layer 309, [0148], Fig. 9; Kim, Fig. 3) formed on the upper gate electrode (Kang, capping layer 309 is formed on the upper buried portion 308 which is an upper gate electrode, hereinafter, upper gate electrode 308, [0148], Fig. 9; Kim, Fig. 3); wherein a top surface of the capping layer, a top surface of the first dielectric layer, and a top surface of the second dielectric layer are coplanar (Kang, a top surface of the second dielectric layer 310L, the top surface of the capping layer 309, and the top surface of the first dielectric layer 311T is coplanar with each other, [0148], Fig. 9; Kim, Fig. 3).
Claim 16, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 10.
Kim/Yedinak/Kang discloses wherein the gate structure 200G is disposed in an active region 104 of the substrate 101 (Kim, 200G is disposed in 104 within 101, para [0048]).
Claim 17, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 10.
Kim/Yedinak/Kang discloses wherein the gate structure 200G is disposed in an isolation region 102 of the substrate 101 (Kim, 200G is disposed in 102 within 101, para [0048]).
Claims 3-4 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang in view of Yedinak in further view of Kocon (US 2004/0256690 A1).
Claim 3, Kim/Kang/Yedinak in further view of Kocon discloses the semiconductor device (Kim, Fig. 3; Kang, fig. 9; Yedinak, Fig. 4A) of claim 2.
Kim/Kang/Yedinak does not explicitly disclose wherein a voltage of the lower gate electrode is greater than a voltage of the upper gate electrode.
However, Kocon discloses (Figs. 2 and 5) a voltage of the lower gate electrode (charge electrodes 212(b), 214(b), 216(b), and 218(b), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) and a voltage of the upper gate electrode (charge electrodes 212(a), 214(a), 216(a), and 218(a), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) can be used to advantageously alter the electric field in para [0042].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable” of gate electrode voltages (result effective at least insofar as dual gate electrodes can be biased in various ranges to alter the electric field (Kocon, para [0042])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed gate electrode voltages or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 4, Kim/Kang/Yedinak in further view of Kocon discloses the semiconductor device (Kim, Fig. 3; Kang, fig. 9; Yedinak, Fig. 4A) of claim 2.
Kim/Kang/Yedinak does not explicitly disclose wherein a voltage difference between the lower gate electrode and the upper gate electrode is greater than 0.3 volts (V).
However, Kocon discloses (Figs. 2 and 5) a voltage difference between the lower gate electrode (charge electrodes 212(b), 214(b), 216(b), and 218(b), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) and the upper gate electrode (charge electrodes 212(a), 214(a), 216(a), and 218(a), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) and demonstrates that dual gate electrodes can be properly biased to alter the electric field to various ranges as described in para [0043].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable” of gate electrode voltages (result effective at least insofar as dual gate electrodes can be biased in various ranges to alter the electric field (Kocon, para [0042])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed gate electrode voltages or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 12, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 10.
Kim/Yedinak/Kang does not explicitly disclose wherein a voltage of the lower gate electrode is greater than a voltage of the upper gate electrode.
However, Kocon discloses (Figs. 2 and 5) a voltage of the lower gate electrode (charge electrodes 212(b), 214(b), 216(b), and 218(b), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) and a voltage of the upper gate electrode (charge electrodes 212(a), 214(a), 216(a), and 218(a), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) can be used to advantageously alter the electric field in para [0042].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable” of gate electrode voltages (result effective at least insofar as dual gate electrodes can be biased in various ranges to alter the electric field (Kocon, para [0042])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed gate electrode voltages or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 13, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 10.
Kim/Yedinak/Kang does not explicitly disclose wherein a voltage difference between the lower gate electrode and the upper gate electrode is greater than 0.3 volts (V).
However, Kocon discloses (Figs. 2 and 5) a voltage difference between the lower gate electrode (charge electrodes 212(b), 214(b), 216(b), and 218(b), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) and the upper gate electrode (charge electrodes 212(a), 214(a), 216(a), and 218(a), para [0039]; Kim, Fig. 3; Yedinak, Fig. 4A) and demonstrates that dual gate electrodes can be properly biased to alter the electric field to various ranges as described in para [0043].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable” of gate electrode voltages (result effective at least insofar as dual gate electrodes can be biased in various ranges to alter the electric field (Kocon, para [0042])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed gate electrode voltages or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang in view of Hsieh (US 2019/0198676 A1).
Claim 9, Kim/Kang discloses the semiconductor device (Kim, Fig. 3; Kang, Fig. 9) of claim 1.
Kim/Kang discloses does not explicitly disclose further comprising: a second barrier layer disposed between the upper gate electrode and the first dielectric layer.
However, Hsieh discloses further comprising: a second barrier layer (Hsieh, top gate dielectric layer 232 further comprises SiO layer 233a, hereinafter, first dielectric layer 233a as well as SiN layer 233b, hereinafter, second barrier layer 233a, [0056], Fig. 10; Kim, Fig. 3) disposed between the upper gate electrode and the first dielectric layer (Hsieh, second barrier layer 233a is disposed between the upper gate electrode 234 and the first dielectric layer 233a, [0056], Fig. 10; Kim, Fig. 3). The combination to utilize a dual layered top gate dielectric structure enables the lower gate to be embedded deeper within the device substrate, reducing current leakage without increasing channel length (Hsieh, [0026]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a dual layered top gate dielectric structure enables the lower gate to be embedded deeper within the device substrate, reducing current leakage without increasing channel length (Hsieh, [0026]).
Claims 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yedinak, further in view of Hsieh.
Claim 15, Kim/Yedinak/Kang discloses the semiconductor device (Kim, Fig. 3; Yedinak, Fig. 4A; Kang, Fig. 9) of claim 14.
Kim/Yedinak/Kang does not explicitly disclose the first dielectric layer and the second dielectric layer comprises different densities.
However, Hsieh in view of Kim/Yedinak/Kang discloses wherein the first dielectric layer (Hsieh, top gate dielectric layer 232 further comprises SiO layer 233a, hereinafter, first dielectric layer 233a as well as SiN layer 233b, hereinafter, second barrier layer 233a, [0056], Fig. 10; Kim, first dielectric layer 110, Fig. 3; Yedinak, Fig. 4A) is spaced apart from the upper gate electrode by the second dielectric layer (Hsieh, first dielectric layer 233a is spaced apart from the upper gate electrode 234 by a second dielectric layer 233b, [0052], Fig. 10; Kim, Fig. 3; Yedinak, Fig. 4A), the first dielectric layer 110 and the second dielectric layer 108 comprises different densities (Kim, first and second barrier layers 108/110 may be made of different materials which inherently will have different densities; first barrier layers 108 are tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN), para [0054] and second barrier layers 110 are tantalum nitride (TaN) or titanium nitride (TiN), para [0056]; Yedinak, Fig. 4A; Hsieh, Fig. 10), and the second dielectric layer directly contacts the lower gate electrode and the upper gate electrode (Hsieh, second dielectric layer 233b directly contacts the upper gate electrode 234, [0052], Fig. 10; Kim, Fig. 3; Yedinak, Fig. 4A); wherein a top surface of the first barrier layer is in contact with the base portion of the second dielectric layer (Kang, top surface of the first barrier layer 310L is in contact with the base portion of the second dielectric layer 310L, [0148], Fig. 9; Kim, Fig. 3; Yedinak, Fig. 4A). The combination to utilize a dual layered top gate dielectric structure enables the lower gate to be embedded deeper within the device substrate, reducing current leakage without increasing channel length (Hsieh, [0026]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a dual layered top gate dielectric structure enables the lower gate to be embedded deeper within the device substrate, reducing current leakage without increasing channel length (Hsieh, [0026]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Huh (US 2021/0242320 A1) discloses (Fig. 5) a semiconductor device including a substrate, first gate electrode, second gate electrode disposed on first gate electrode, active region, and isolation region.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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